Broadcom BCM5722 - Table 239: DMA Flags Register for TCP Segmentation (Offset 0 Xcec)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R TCP Segmentation Control Registers Page 274
DMA FLAGS REGISTER FOR TCP SEGMENTATION (OFFSET 0XCEC)
Table 239: DMA Flags Register for TCP Segmentation (Offset 0xCEC)
Bit Field Description Init Access
31:20 Reserved – 0 RO
19 MBUF offset valid MBUF offset valid.
When this bit is set, the RDMA engine will DMA the data
into the TXMBUF starting at an offset specified in the
Length/Offset register (see “Length/Offset Register for
TCP Segmentation (Offset 0xCE8)” on page 273).
0R/W
18 Last Fragment Last Fragment. This bit is passed transparently to the
SDC.
When this bit is set, the SDC will inform the HC to
increment the Send Ring Consumer Index.
• The bit is always set by hardware if no firmware
assisted TCP segmentation occurs.
• Otherwise, firmware sets it at the end of fragmentation.
0R/W
17 No Word Swap No Word Swap.
Set to disable endian word swap on data from PCI bus.
0R/W
16 Reserved The bit can be written/read, but has no chip impact. 0 RO
15:14 MAC source address
insertion
MAC source address insertion.
This 2-bit field determines which of the four MAC
addresses should be inserted into the frame.
0R/W
13 MAC source address
insertion
MAC source address insertion.
Indicates that the predetermined source address is
inserted into the Ethernet header of the frame.
0R/W
12 TCP/UDP checksum
enable
TCP/UDP checksum enable. 0 R/W
11 IP checksum enable IP checksum enable. 0 R/W
10 Force RAW checksum
enable
Force RAW checksum enable. 0 R/W
9 Checksum offset Checksum offset.
• When bit 10 is set to 1 and this bit is 0, the checksum
will start at offset of 14.
• When bit 10 is set to 1 and this bit is 1, the checksum
will start at offset of 0 (i.e., checksum calculation will be
performed on all data written into TXMBUF).
0RO
8 Reserved The bit can be written/read, but has no chip impact. 0 R/W
7 VLAN Tag Present VLAN Tag Present. Indicates that the VLAN tag should
be copied into the Frame Header by the DMA engine.
0R/W
6 Force Interrupt Force Interrupt. Following the completion of this DMA, a
host interrupt is generated.
0R/W
5 Last BD in Frame Last BD in Frame. 0 R/W
4 Coalesce Now Coalesce Now. Pass through Send Buffer Descriptor flag. 0 R/W
3 Reserved The bit can be written/read, but has no chip impact. 0 RO