Broadcom BCM5722 - Table 84: Integrated MAC WOL Mode Control Registers

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Wake on LAN Mode/Low-Power Page 168
Integrated MACs
Table 84 lists the WOL mode control registers in the BCM5722 Ethernet controllers.
Table 84: Integrated MAC WOL Mode Control Registers
Register Bit(s) Name Description Cross Reference
WOL_Pattern_
Pointer
All This register points to an internal
memory location. Programmers should
calculate pointer value by dividing a
base address by 8.
“WOL Pattern Pointer Register
(Offset 0x430)” on page 249.
WOL_Pattern_
Configuration
Length The number of memory arbiter clock
cycles needed to read X bytes in the RX
stream/frame.
“WOL Pattern Configuration
Register (Offset 0x434)” on
page 250.
Offset The number of bytes into the RX
stream/frame to begin the pattern
comparison.
Ethernet_MAC_
Mode
Port_Mode This bit field specifies the type of
interface the BCM5722 Ethernet
controller port is currently using: MII,
GMII, or none.
“Ethernet MAC Mode Register
(Offset 0x400)” on page 245.
Magic_Packet_
Detection
Enable WOL pattern filtering.
Promiscuous_mode All frames are forwarded, without any
filtering, when this bit is enabled.
PCI Clock_Control TX RISC_Clock_Disable Disable the clock to the transmit CPU. “PCI Clock Control Register
(Offset 0x74)” on page 207.
RX RISC_Clock_Disable Disable the clock to the receive CPU.
Alternate_Clock_Source Use an alternate clock as a reference,
rather than the PLL 133.
PLL133 Disable the 133-MHz phase-locked
loop.
Misc Local Control Misc_Pin_0_Output GPIO pin 0. “Miscellaneous Local Control
Register (Offset 0x6808)” on
page 336.
Misc_Pin_0_Output_
Enable
When asserted, MAC drives pin output.
Misc_Pin_1_Output GPIO pin 1.
Misc_Pin_1_Output_
Enable
When asserted, MAC drives pin output.
Misc_Pin_2_Output GPIO pin 2.
Misc_Pin_2_Output_
Enable
When asserted, MAC drives pin output.
Power Management
Control/Status
PME_Enable Enable the BCM5722 Ethernet
controller to assert PME on PCI bus.
“Power Management Control/
Status Register (Offset 0x4C)”
on page 198.
Power_State Set the ACPI power state: D0, D3.