BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 169 Wake on LAN Mode/Low-Power Document 5722-PG101-R
WOL DATA FLOW DIAGRAM
The BCM5722 Ethernet controller and PHY are both configured for WOL mode. The process is as follows:
1. Clear the PME_Status bit in the “PMCSR-BSE Register (Offset 0x4E)” on page 198. This bit must be cleared, so the
PME interrupt is not immediately generated once the NIC is moved to the D3 state. The bit could be asserted from a
previous D3–D0 transition.
2. Set the Mask_PCI_Interrupt_Output bit in the Miscellaneous_Host_Control register (see “Miscellaneous Host Control
Register (Offset 0x68)” on page 204). This bit should be set, so the BCM5722 Ethernet controller does not generate
interrupts during the WOL configuration of the PHY. The device driver’s ISR may attempt to reset and reconfigure the
PHY as part of an error recovery code path.
3. If host software needs to place the NIC into D3 cold state, the following step is necessary. Set the
10_Base_TX_Half_Duplex and 10_BASE_TX_Full_Duplex Capability bits, in the “Auto-Negotiation Advertisement
Register (PHY_Addr = 0x1, Reg_Addr = 04h)” on page 419. Clear the 100_BASE_TX_Full_Half_Duplex and
100_BASE_TX_Full_Duplex Capability bits, in the “Auto-Negotiation Advertisement Register (PHY_Addr = 0x1,
Reg_Addr = 04h)” on page 419. Clear the 1000_BASE_TX_Half_Duplex and 1000_BASE_TX_Full_Duplex Capability
bits, in the “1000BASE-T Control Register (PHY_Addr = 0x1, Reg_Addr = 09h)” on page 425. The link partner will now
only be able to auto-negotiate for 10-Mbps speed full/half-duplex.
4. Set the Restart_Auto_Negotiation bit in the “MII Control Register (PHY_Addr = 0x1, Reg_Addr = 00h)” on page 415. The
integrated PHY and link partner will now reconfigure for 10 Mbps wire speed. Essentially, 10 Mbps link must be auto-
negotiated or forced.
5. Disable the FHDE, RDE, TDE bits of the “Ethernet MAC Mode Register (Offset 0x400)” on page 245”, and on-chip
RISCs.
6. Host software must write the signature 0x4B657654 to internal memory address 0x0B50. Check for one’s complement
of 0x4B657654.
7. Enable the Wake_On_LAN bit in the “Auxiliary Control Register (PHY_Addr = 0x1, Reg_Addr = 18h, Shadow = 010,
Power Control)” on page 447.
8. For Interesting Packet WOL Only: Set up the Interesting Packet pattern in BCM5722 Ethernet controller local memory.
9. For Interesting Packet WOL Only: Write a pointer value to the “WOL Pattern Pointer Register (Offset 0x430)” on
page 249. This register uses a normalized pointer value, not a device base address. The value written to this register is
BCM5700_BASE_ADDR/8. The base address must be a specific location in local memory: 0x8000, 0xC000, or 0xD000.
The choice of memory location depends upon other MAC configurations, and the selection is not arbitrary.
10. For Interesting Packet WOL Only: Write the Offset field in the “WOL Pattern Configuration Register (Offset 0x434)” on
page 250. The WOL pattern checker will position into received frames on two-byte intervals. The pattern checker
compares two bytes in parallel, so host software should program the offset field accordingly. Host software may perceive
this unit as OFFSET_BYTE/2 units.
11. For Interesting Packet WOL Only: Write the Length field in the “WOL Pattern Configuration Register (Offset 0x434)” on
page 250. The length value is specified in terms of Memory Arbiter clock cycles, not bytes/words/dwords. A
comprehensive discussion of how the clock cycles are calculated will be presented.
12. Set the Port_Mode field in the “Ethernet MAC Mode Register (Offset 0x400)” on page 245 to GMII mode. These bits
enable the GMII between the MAC and internal PHY.
13. For Interesting Packet WOL Only: Enable the ACPI_Power-On bit in the “Ethernet MAC Mode Register (Offset 0x400)”
on page 245. This bit will enable logic for D3 hot/cold transitions to D0 ACPI state. The MAC will also be capable of
asserting PME on the PCI bus.
14. For Interesting Packet WOL Only: Enable the Magic_Packet_Detection bit in the “Ethernet MAC Mode Register (Offset
0x400)” on page 245. The WOL logic will compare RX frames for Magic Packet patterns.
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