Broadcom BCM5722 - Table 365: Miscellaneous Clock Control Register (Offset: 0 X68 A0)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 351 Wake-on-LAN Registers Document 5722-PG101-R
MISCELLANEOUS CLOCK CONTROL REGISTER (OFFSET: 0X68A0)
This register is applicable to BCM5722, BCM5755, BCM5755M, BCM5756M, BCM5757 devices only. Some of the bits in
this register are initialized by hard_reset.
Table 365: Miscellaneous Clock Control Register (Offset: 0x68A0)
Bit Field Description Reset Init Access
31:6 Reserved – 0 RO
5 TPM Clock Shutoff
Enable
This bit is used to enable the TPM clock shutoff when
TPM is in IDDQ. When TPM is enabled (i.e. not in
IDDQ), this bit has no impact with TPM clock.
Hard_Reset 1 R/W
4 Disable Fast ACQ This bit is used to disable Fast Acquisition Method
• 1 = Disable
• 0 = Enable
Fast acquisition method will acquire and lock 4 times
faster than normal acquisition mode. This bit is mainly
used as a safety fallback should the fast acquisition
mode causes some unforeseen glitches. If lock time is
not an issue, it is recommended to assert
disable_fast_acq. It should be changed when
Frequency Multiplier Enable is not set.
Hard_Reset 0 R/W
3 APD Slow Clock
Enable
• 1 = Enable LAN core clock slowdown in auto-power
down mode
• 0 = Disable LAN core clock slowdown in auto-power
down mode
This bit is used to control whether to slow down LAN
core clock or not when entering the airplane mode. If
this bit is 0, GPHY DLL will not be allowed to shut down
in Airplane mode. If LAN core clock is slowed down, the
clock speed will depend upon PCI Clock Control
register bit20. If bit20 is 1, the core clock will be 6.25
MHz. Otherwise, it is 12.5 MHz.
It is not recommended for software or f/w to turn this bit
on because doing so may overflow RDMA FIFO when
the device enters the airplane mode and the host is
sending the packet. Instead, software or f/w can control
the core clock speed by PCI Clock Control register
(0x74) bit12. Meanwhile, GPHY MII registers should be
configured to be 10/100Mbps capable. It will prevent
MAC FIFO overflow when exiting the airplane mode.
Hard_Reset 0 R/W
2 TPM Power-Saving
Enable
• 1 = Enable TPM core clock slowdown if TPM is idle
• 0 = Disable TPM core clock slowdown if TPM is idle
If this bit is enabled, TPM core clock will vary with TPM
status. If it’s in IDLE, both Flash and TPM will run the
same clock at 6.25 MHz. If TPM is active, both Flash
and TPM will run the same clock at 62.5 MHz. If this bit
is 0, both TPM and Flash will run the same clock at 62.5
MHz no matter TPM is idle or active.
Hard_Reset 0 R/W