Broadcom BCM5722 - Table 448: Data Link ACK Timeout Register (Offset 0 X7 D24); Table 449: Power Management Threshold Register (Offset 0 X7 D28); Table 450: Retry Buffer Write Pointer Debug Register (Offset 0 X7 D2 C); Table 451: Retry Buffer Read Pointer Debug Register (Offset 0 X7 D30)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R PCIe Registers Page 400
DATA LINK ACK TIMEOUT REGISTER (OFFSET 0X7D24)
POWER MANAGEMENT THRESHOLD REGISTER (OFFSET 0X7D28)
This register is reset by either POR or GRC (soft) reset.
RETRY BUFFER WRITE POINTER DEBUG REGISTER (OFFSET 0X7D2C)
RETRY BUFFER READ POINTER DEBUG REGISTER (OFFSET 0X7D30)
Table 448: Data Link ACK Timeout Register (Offset 0x7D24)
Bit Field Description Init Access
31:11 Reserved Write as 0, ignore when read. 0 RO
10:0 ACK Latency Timeout
Value
ACK latency timeout value in data link layer clock cycles
(8 ns).
0xff R/W
Table 449: Power Management Threshold Register (Offset 0x7D28)
Bit Field Description Init Access
31:24 Reserved Write as 0, ignore when read. 0 RO
23:20 D3C Re-enter
Threshold (CQ10452)
Minimum time in us before re-enter to L1 link state.
• 0x8 R/W
19:16 D3C Exit Threshold
(CQ10452)
Minimum time in us that the link must stay in L1. 0x2 R/W
15:8 L1 Threshold Idle time before entering L1 low-power state (unit = 256 ns). 0x62 R/W
7:0 L0s Threshold Idle time before entering L0s low-power state (unit = 16 ns). 0xfa R/W
Table 450: Retry Buffer Write Pointer Debug Register (Offset 0x7D2C)
Bit Field Description Init Access
31:11 Reserved Write as 0, ignore when read. 0 RO
10:0 Retry Buffer Write
Pointer
Address of next DWORD to be written into retry buffer
RAM.
0R/W
Table 451: Retry Buffer Read Pointer Debug Register (Offset 0x7D30)
Bit Field Description Init Access
31:11 Reserved Write as 0, ignore when read. 0 RO
10:0 Retry Buffer Read
Pointer
Address of next DWORD to be read from retry buffer
RAM.
0R/W