Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Flow-Through Queues Page 328
RXMBUF CLUSTER FREE ENQUEUE REGISTER (OFFSET 0X5CC8)
A write to this register frees a cluster of RXMBUFs. The host CPU uses this register to deallocate RXMBUFs after it has
processed the received ASF message.
RDIQ FTQ WRITE/PEEK REGISTER (OFFSET 0X5CFC)
The host CPU uses this register to get the RXMBUF cluster pointers if the received packet requires the attention of the CPU.
This could be an ASF or ACPI packet.
• A write to this register will modify the head of the RDIQ FTQ entry.
• A read of this register will peek at the head of the RDIQ FTQ entry.
• When the Valid bit is 1 and the Pass bit is 0, the CPU can take the RXMBUF cluster pointers to access the received
packet (see Table 335).
• When the CPU writes a 1 to the Skip bit, the hardware will pop the head of the queue entry (see Table 335).
Note: This register is not applicable to the BCM5906 device.
Table 333: RXMBUF Cluster Free Enqueue Register (Offset 0x5CC8)
Bit Field Description Init Access
31:18 Reserved – 0x0 W/O
17:9 Head RXMBUF Pointer Specifies the first MBUF of the RXMBUF cluster for the
received packet to be freed.
0x00 W/O
8–0 Tail RXMBUF Pointer Specifies the last MBUF of the RXMBUF cluster for the
received packet to be freed.
0x00 W/O
Table 334: RDIQ FTQ Write/Peek Register (Offset 0x5CFC)
Bit Field Description Init Access
31:21 Reserved – 00000000000 RO
20 Valid Bit Set only if the head of the RDIQ entry is valid (i.e., the
queue is non-empty). See Table 335.
0R/W
19 Skip Bit If this bit is set, the head of the RDIQ entry will be popped.
The read pointer will be incremented. See Table 335.
0R/W
18 Pass Bit This bit is 0 if the RDIQ head entry is intended for the
CPU. It prevents the entry to be serviced by WDMA. See
Table 335.
0R/W
17:9 Head RXMBUF Pointer Specifies the first MBUF of the RXMBUF cluster for the
received packet.
000000000 RO
8–0 Tail RXMBUF Pointer It specifies the last MBUF of the RXMBUF cluster for the
received packet.
000000000 RO