Broadcom BCM5722 - Table 363: Chip Mode Register (Offset: 0 X6898)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 349 Wake-on-LAN Registers Document 5722-PG101-R
CHIP MODE REGISTER (OFFSET: 0X6898)
30:0 FastBoot Program
Counter
This field is used by the CPU to keep track of the location of the phase
1 bootcode in RX MBUF. These bits behave identical to bit 31 in that
they have no effect on state machine operation and they are cleared
only by a power-on reset.
0R/W
Table 363: Chip Mode Register (Offset: 0x6898)
Bit Field Description Init Access
31:11 Reserved Reserved 0 RO
10 Chip_mode_ov
• 1 = Override the chip_mode using the
chip_mode_wr
• 0 = Not allowed to override the chip_mode
0R/W
9:5 Chip_mode_wr[3:0] The write value of chip mode 0 R/W
4:0 Chip_mode_rd[3:0] The read value of chip mode 0 RO
Table 362: Fast Boot Program Counter Register (Offset 0x6894) (Cont.)
Bit Field Description Init Access