BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 231 PCIe-Enhanced Capabilities Document 5722-PG101-R
DEVICE SERIAL NO UPPER DW REGISTER (OFFSET 0X168)
POWER BUDGETING ENHANCED CAPABILITY HEADER REGISTER (OFFSET 0X16C)
POWER BUDGETING DATA SELECT REGISTER (OFFSET 0X170)
Table 172: Device Serial No Upper DW Register (Offset 0x168)
Bit Field Description Init Access
31:8 Upper MAC Address This field is 0xFFFFFF after reset.
If bit 23 of 0x7c04 is 1, this field is programmable
using PCI memory write cycles or the indirect
register access method via configuration writes to
0x78 and 0x80.
If bit 23 of 0x7c04 is 0, this register is not writable. In
addition, the content of the MAC Address register is
copied into this register automatically.
Bootcode sets bit 23 of 0x7c04 after it has
programmed the MAC address into registers 0x410
and 0x414. This ensures that when the driver
changes the value at offset 0x410 or 0x414, the
content of this register remains unchanged.
0xFFFFFF Config-RO
Memory-RW
7:0 Reserved By default this field is 0xFF after reset.
If bit 23 of 0x7c04 is 1, this field is programmable
using PCI memory write cycles or the indirect
register access method via configuration writes to
0x78 and 0x80.
If bit 23 of 0x7c04 is 0, this field is read-only.
0xFF Config-RO
Memory-RW
Note: Power Budgeting registers do not apply to the BCM5906 device.
Table 173: Power Budgeting Enhanced Capability Header Register (Offset 0x16C)
Bit Field Description Init Access
31:20 Next Capability Offset No other PCIe Capability Structure 0x000 RO
19:16 Revision ID 0x1 RO
15:0 PCIe Capability ID PCIe Power Budget Capability ID Register 0x0004 RO
Table 174: Power Budgeting Data Select Register (Offset 0x170)
Bit Field Description Init Access
31:8 Reserved – 0x000000 RO
7:0 Data Select Index Power Budgeting Data reported through the Data register 0x00 RW
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