Broadcom BCM5722 - Table 362: Fast Boot Program Counter Register (Offset 0 X6894)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Wake-on-LAN Registers Page 348
FAST BOOT PROGRAM COUNTER REGISTER (OFFSET 0X6894)
27 CLKREQ# Disable CLKREQ# disable This bit is reset by hard_reset. 0 R/W
26 energy_det_sel 1: Select combination of s/w energy_del bit or h/w energy_det
debounce signal; see details on register 0x68.
0: select h/w energy_det debounce signal.
This bit is reset by POR only.
0R/W
25 Super Airplane mode
enable
Defines how the LOW_POWER_MODE behaves:
1 = Super Airplane mode Enable
0 = Normal LOWER_POWER_MODE
This bit is reset by POR only, and its original name is Super Airplane
Mode.
0R/W
24 Reserved 0R/O
23 vcpu_reset Virtual CPU reset.
1: Reset virtual CPU block. The boot code will be fetched and
executed from the beginning of EEPROM image. This reset is self-
clearing.
0: Normal operation
This bit is cleared by hard reset.
0R/W
22 vcpu_halt Virtual CPU suspend.
1: Halt the virtual CPU after the current instruction is executed. When
this bit is cleared, the virtual CPU will resume from its last suspended
instruction.
0: Normal operation
This bit is cleared by hard reset.
0R/W
21 vcpu_grc_reset_disable GRC reset mask for the virtual CPU block.
1: Mask the GRC reset going to the virtual CPU. This bit is useful
during driver load and unloads, when the boot code does not need to
be re-executed (MAC address will be reset?).
0: Normal operation
This bit is cleared by hard reset.
0R/W
20:0 Reserved 0R/O
Note: This register is not applicable to the BCM5906 device.
Table 362: Fast Boot Program Counter Register (Offset 0x6894)
Bit Field Description Init Access
31 FastBoot Enable This bit is used by the CPU to keep track of whether or not there is
valid phase 1 bootcode stored in the RX MBUF. If the bit is set, then
RXMBUF contains valid bootcode. Otherwise, it is assumed that
RXMBUF does not contain valid bootcode. This bit is reset only by a
power-on reset. The state of this bit has no effect on state machines
within the device. It is used by the CPU to track bootcode status.
0R/W
Table 361: Miscellaneous Cable Sense Control Register (Offset: 0x6890)—BCM5906 Only (Cont.)
Bit Field Description Init Access