BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 141 Power Management Document 5722-PG101-R
REGISTER QUICK CROSS REFERENCE
The BCM5722 Ethernet controller power management registers are listed in Table 55.
Table 55: Power Management Registers
Register Bit Description Cross Reference
Misc Local Control Misc_Pin_0_Output GPIO pin 0 “Miscellaneous Local Control
Register (Offset 0x6808)” on
page 336.
Misc Local Control Misc_Pin_0_Output_Enable When asserted, MAC drives
pin output
Misc Local Control Misc_Pin_1_Output GPIO pin 1
Misc Local Control Misc_Pin_1_Output_Enable When asserted, MAC drives
pin output
Misc Local Control Misc_Pin_2_Output GPIO pin 2
Misc Local Control Misc_Pin_2_Output_Enable When asserted, MAC drives
pin output
Misc Host Control Enable_Clock_Control_Register
PCI Clock_Control TX RISC_Clock_Disable Disable the clock to the
transmit CPU
“PCI Clock Control Register
(Offset 0x74)” on page 207.
PCI Clock_Control RX RISC_Clock_Disable Disable the clock to the
receive CPU
PCI Clock_Control Select_Alternate_Clock Use an alternate clock as a
reference, rather than the PLL
133
PCI Clock_Control PLL133 Disable the 133-MHz phased
locked loop
PCI Power
Management
Control/Status
PME_Enable – “Power Management Control/
Status Register (Offset 0x4C)” on
page 198.
PCI Power
Management
Control/Status
Power_State –
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