Broadcom BCM5722 - Table 177: Firmware Power Budgeting Register 1 (Offset 0 X17 C); Table 178: Firmware Power Budgeting Register 2 (Offset 0 X17 E)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 233 PCIe-Enhanced Capabilities Document 5722-PG101-R
FIRMWARE POWER BUDGETING REGISTER 1 (OFFSET 0X17C)
FIRMWARE POWER BUDGETING REGISTER 2 (OFFSET 0X17E)
Table 177: Firmware Power Budgeting Register 1 (Offset 0x17C)
Bit Field Description Init Access
15:13 Power Rail Specifies the power rail of the operating condition
12V (000)
3.3V (001)
1.8V (010)
Thermal (111)
0x0 RW from Internal CPU
Config RO
Memory RW
12:10 Type Specifies the type of the operating condition
PME Aux (000)
Auxiliary (001)
Idle (010)
Sustained (010)
Maximum (111)
0x0 RW from Internal CPU
Config RO
Memory RW
9:8 PM State Specifies the power management state of operating
condition—D0, D3
0x0 RW from Internal CPU
Config RO
Memory RW
7:0 Base Power Specifies in Watts the base power value in a given
operating conditions
0x0 RW from Internal CPU
Config RO
Memory RW
Table 178: Firmware Power Budgeting Register 2 (Offset 0x17E)
Bit Field Description Init Access
15:13 Power Rail Specifies the power rail of the operating condition
12V (000)
3.3V (001)
1.8V (010)
Thermal (111)
0x0 RW from Internal CPU
Config RO
Memory RW
12:10 Type Specifies the type of the operating condition
PME Aux (000)
Auxiliary (001)
Idle (010)
Sustained (010)
Maximum (111)
0x0 RW from Internal CPU
Config RO
Memory RW
9:8 PM State Specifies the power management state of operating
condition—D0, D3
0x0 RW from Internal CPU
Config RO
Memory RW
7:0 Base Power Specifies in Watts the base power value in a given
operating conditions
0x0 RW from Internal CPU
Config RO
Memory RW