Broadcom BCM5722 - RX RISC State Register (Offset 0 X5004); Table 317: RX RISC State Fields (Offset 0 X5004)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R RX RISC Registers Page 318
RX RISC STATE REGISTER (OFFSET 0X5004)
The RX RISC State register reports the current state of the RX RISC and, if halted, gives reasons for the halt. There are four
categories of information; informational (read-only), informational (write-to-clear), disable-able halt conditions (write-to-
clear), and non-disable-able halt conditions (write-to-clear).
7 Enable Watchdog Enables watchdog interrupt state machine. Used in
conjunction with Watchdog Clear register, Watchdog
Saved PC register and Watchdog Vector register.
Cleared on reset and Watchdog interrupt.
0RW
6 ROM Fail Asserted on reset. Cleared by ROM code after it
successfully loads code from NVRAM. Afterwards, this bit
can be used by software for any purpose.
1RW
5 Enable Data Cache Enables the data cache. Cleared on reset.
Note: Firmware developers should take care to clear
this bit before polling internal SRAM memory locations,
because the RX RISC processor uses a two-element
LRU caching algorithm, which is not affected by writes
from the PCI interface.
0RW
4 Enable Write Post
Buffers
Enables absorption of multiple SW operations for SRAM
and register writes. When this bit is disabled, only one
write at a time will be absorbed by the write post buffers.
Cleared on reset.
Note: Setting this bit on the BCM5705, BCM5721, and
BCM5751 may cause unpredictable behavior.
0RW
3 Enable Page 0 Instr
Halt
When set, instruction references to the first 256 bytes of
SRAM force the RX RISC to halt and cause bit 4 in the
RX RISC state register to be latched. Cleared on reset
and Watchdog interrupt.
0RW
2 Enable Page 0 Data
Halt
When set, data references to the first 256 bytes of SRAM
force the RX RISC to halt and cause bit 3 in the RX RISC
state register to be latched. Cleared on reset and
Watchdog interrupt.
0RW
1 Single-Step RX RISC Advances the RX RISC’s PC for one cycle. If halting
condition still exists, the RX RISC will again halt;
otherwise, it will resume normal operation.
0RW
0 Reset RX RISC Self-clearing bit which resets only the RX RISC. 0 RW
Table 317: RX RISC State Fields (Offset 0x5004)
Bit Field Description Init Access
31 Blocking read A blocking data cache miss occurred, causing the RX
RISC to stall while data is fetched from external (to the
RX RISC) memory. This is intended as a debugging tool.
No state is saved other than the fact that the miss
occurred.
0W2C
30 MA request FIFO
overflow
MA_req_FIFO overflowed. The RX RISC is halted on this
condition.
0W2C
29 MA data/bytemask
FIFO overflow
MA_datamask_FIFO overflowed. The RX RISC is halted
on this condition.
0W2C
Table 316: RX RISC Mode Register Fields (Offset 0x5000) (Cont.)
Bit Field Description Init Access