BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 319 RX RISC Registers Document 5722-PG101-R
28 MA outstanding read
FIFO overflow
MA_rd_FIFO overflowed. The RX RISC is halted on this
condition.
0W2C
27 MA outstanding write
FIFO overflow
MA_wr_FIFO overflowed. The RX RISC is halted on this
condition.
0W2C
26:16 Reserved Always 0. 0 RO
15 Instruction fetch stall The processor is currently stalled due to an instruction
fetch.
0RO
14 Data access stall The processor is currently stalled due to a data access. 0 RO
13:11 Reserved Always 0. 0 RO
10 RX RISC Halted The RX RISC was explicitly halted via bit 10 in the RX
RISC Mode register.
0RO
9 Register address trap A signal was received from the Global Resources block
indicating that this processor accessed a register location
that triggered a software trap. The GRC registers are
used to configure register address trapping.
0W2C
8 Memory address trap A signal was received from the Memory Arbiter indicating
that some internal block, possibly this processor,
accessed a memory location that triggered a software
trap. The MA registers are used to configure memory
address trapping.
0W2C
7 Bad Memory Alignment Load or Store instruction was executed with the least
significant two address bits not valid for the width of the
operation (e.g., Load word or Load Half-word from an odd
byte address).
0W2C
6 Invalid Instruction
Fetch
Program Counter (PC) is set to invalid location in
processor address space. See“Memory Maps and Pool
Configuration” on page 101 for details about unmapped
areas in the CPU address space.
0W2C
5 Invalid Data Access Data reference to illegal location. See “Memory Maps and
Pool Configuration” on page 101 for details about
unmapped areas in the CPU address space.
0W2C
4 Page 0 Instruction
Reference
When enabled in mode register, indicates the address in
the PC is within the lower 256 bytes of SRAM.
0W2C
3 Page 0 Data Reference When enabled in mode register, indicates data reference
within lower 256 bytes of SRAM.
0W2C
2 Invalid Instruction Invalid instruction fetched. 0 W2C
1 Halt Instruction
Executed
A halt-type instruction was executed by the RX RISC. 0 W2C
0 Hardware Breakpoint When enabled in mode register, indicates hardware
breakpoint has been reached.
0W2C
Table 317: RX RISC State Fields (Offset 0x5004) (Cont.)
Bit Field Description Init Access
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