Broadcom BCM5722 - Table 200: MI Communication Register (Offset 0 X44 C); Table 201: MI Status Register (Offset 0 X450)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 251 Ethernet MAC Control Registers Document 5722-PG101-R
MI COMMUNICATION REGISTER (OFFSET 0X44C)
This register is used to communicate with a transceiver device through the MII/GMII management interface signals MDIO
and MDC. To complete a transaction, the register values are configured for the operation, and the Start bit (bit 29) is set.
When the transaction completes, the Start bit will be cleared by the device. The Read Failed bit (bit 28) can be used to
determine an incomplete read transaction. The Transaction Data field should be ignored when the Read Failed bit is set.
MI STATUS REGISTER (OFFSET 0X450)
This register contains status from a PHY using the management interface. It is obtained during autopolling and will not be
valid if autopolling is disabled. If auto-polling is not enabled, bit 0 must be set to enable link to the MAC state machines.
Table 200: MI Communication Register (Offset 0x44C)
Bit Field Description Init Access
31:30 Reserved Always 0. 0 RO
29 Start/Busy Set this bit to start a transaction. While it is high, it indicates
that the current transaction is still ongoing. If enabled,
generates an attention via the EMAC Status Register MI
Completion bit (bit 22).
0R/W
28 Read failed When set, the transceiver device did not driver the bus
during the attempted read transaction. Valid after the Start/
Busy bit is cleared.
0RO
27:26 Command These bits specify the transaction type:
• 11 = Undefined.
• 10 = Read command.
• 01 = Write command.
• 00 = Undefined.
00b R/W
25:21 PHY Addr PHY Address. 0000b R/W
20:16 Register Address Address of the register to be read or written. 0000b R/W
15:0 Transaction Data When configured for a write command, the data stored at
this location is written to the PHY at the specified PHY and
register address. During a read command, the data
returned by the PHY is stored at this location.
0R/W
Table 201: MI Status Register (Offset 0x450)
Bit Field Description Init Access
31:2 Reserved Always 0. 0 RO
1 Mode10 Mbps When read, a value of 1 indicates the transceiver device is
operating in 10 Mbps mode.
0R/W
0 Link status The bit will generate an attention if enabled. Indicates
status of the link on the transceiver device. When read, a
value of 1 indicates the transceiver is linked.
0R/W