Broadcom BCM5722 - Table 152: Message Control Register (Offset 0 Xea)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Message Signaled Interrupts Capabilities Page 222
MESSAGE CONTROL REGISTER (OFFSET 0XEA)
This 16-bit register provides system software control over MSI. After reset, MSI is disabled (bit 0 is cleared) and the function
requests servicing via its INTA
pin. System software can enable MSI by setting bit 0 of this register to a 1. System software
is permitted to modify the Message Control register’s read/write bits and fields. A device driver is not permitted to modify the
read/write bits and fields.
Table 152: Message Control Register (Offset 0xEA)
Bit Field Description Init Access
15:8 Reserved – 0 RO
7 64-bit Address Capable Indicates that the device is capable of generating a 64-bit
message address. This bit is hardwired to 1 because the device
is 64-bit message address capable.
1RO
6:4 Multiple Message
Enable
System software writes to this field to indicate the number of
allocated messages (equal to or less than the number of
requested message). The number of allocated messages is
aligned to a power of two. When MSI is enabled, a device will
be allocated at least one message. The encoding is as follows:
Encoding # Messages Allocated
000 1
001 2
010 4
011 8
100 16
101 32
110 Rsvd
111 Rsvd
000 R/W
3:1 Multiple Message
Capable
System software reads this field to determine the number of
requested messages. The number of requested messages
must be aligned to a power of two. The encoding is as follows:
Encoding # Messages Allocated
000 1
001 2
010 4
011 8
100 16
101 32
110 Rsvd
111 Rsvd
000 RO
0 MSI Enable If 1, the function is permitted to use MSI to request service and
is prohibited from using the INTA
pin. If 0, the device is
prohibited from using MSI. System software sets this bit to
enable MSI. A device driver is prohibited from writing to this bit.
0R/W