Broadcom BCM5722 - Table 366: Power Management Debug Register (Offset: 0 X68 A4)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Wake-on-LAN Registers Page 352
POWER MANAGEMENT DEBUG REGISTER (OFFSET: 0X68A4)
1 Frequency
multiplier Enable
• 1 = Enable frequency multiplier to generate a 62.5-
MHz clock from XTAL clock
• 0 = Disable Frequency multiplier
This bit should be used together with bit0.
Before software selects frequency multiplier, this bit
should be set first, then set bit0.
Bit1 Bit0 Clock Source
0 0 GPHY DLL
0
1 Illegal
1
0 Illegal
1
1 Frequency Multiplier
POR 0 R/W
0 TPM Clock Select
• 1 = Select frequency multiplier clock
• 0 = Select GPHY DLL clock
If both bit1 and this bit are set, TPM core clock will use
frequency multiplier as the source clock of 62.5 MHz.
Otherwise, GPHY DLL will be the source clock of 62.5
MHz. If bit2 is set and TPM is idle, XTAL will be the
source clock of Flash and TPM.
Note: Software or firmware should select frequency
multiplier as TPM source clock when GPHY DLL is
powered on. Otherwise, it will not be functional.
POR 0 R/W
Table 366: Power Management Debug Register (Offset: 0x68A4)
Bit Field Description Reset Init Access
31 Powerdown Restart
PCIE PLL Enable
• 1 = Enable restart PCIe PLL when PCIe PLL is locked
up in the powerdown mode, or IDDQ mode, or during
POR, or any combinations.
• 0 = Disable restart PCIe PLL in powerdown mode.
Hard_
Reset
0R/W
30 Normal Restart PCIE
PLL Enable
• 1 = Enable restart PCIe PLL in normal mode.
Firmware needs to write 1 and then write 0 to restart
it (pulse restart).
• 0 = Disable restart PCIe PLL in normal mode.
Hard_
Reset
0R/W
29 PCIE clocks override
with Core_clock
These feature is only to be used in debug mode. Set this
bit in conjunction of bit 16 at 0x7D00 is to allow PCIe
register access when the chip is in power saving idle
mode, or when the PCIe SerDes PLL can not come up
from low power mode.
• 1 = To override PCIe TL/DL/PL clocks with core_clock
when chip is low power mode and PCIe SerDes PLL
is down.
• 0 = No Override
Hard_
Reset
0R/W
28:17 Reserved – 0 RO
Table 365: Miscellaneous Clock Control Register (Offset: 0x68A0) (Cont.)
Bit Field Description Reset Init Access