Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R MSI Page 182
HOST COALESCING ENGINE
After the host coalescing engine updates the status block on the host (due to receive indication, transmit completion, and so
on), it either generates an interrupt or writes a MSI message if MSI is enabled. The least significant 3-bits of the MSI message
originating from host coalescing block is configurable and can be configured by programming bits 4, 5, and 6 of the
Host_Coalesing_Mode register. The default of these bits is zeros.
FIRMWARE
The BCM5722 Ethernet controller provides a way for firmware executed by RX RISC to generate MSI messages. Firmware
can generate MSI messages by using MSI_FIFO_Access register (Offset 0x6008). For example, if firmware wants to
generate an MSI message with least significant 3-bit as 0x2, it will write 2 to MSI_FIFO_Access register. It also needs to
verify that the MSI message is written successfully by reading back MSI_FIFO_Access Overflow. If this bit is zero, then the
MSI message is encoded successfully and will be sent to HOST. Otherwise, the message is not encoded.
Note: Without any special firmware supporting multiple MSIs, the device can generate only 1 MSI message
even though the device requests for 8 MSI messages through Multiple Message Capable field (bits 3:1) of
Message Control register (offset 0x5A). The least significant 3-bits of the MSI message generated by the
device are always taken from bits 6:4 of Host_Coalesing_Mode register (offset 0x3C00).
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