Broadcom BCM5722 - Table 353: MDI Control Register (Offset 0 X6844)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R General Control Registers Page 342
MDI CONTROL REGISTER (OFFSET 0X6844)
The control register for handling the Management Data Interface, which used to communicate between the physical layer
and management layer.
SERIAL EEPROM DELAY REGISTER (OFFSET 0X6848)
This 32-bit R/W register specifies the delay between the EEPROM access in 15 ns interval and is used for VPD access.
Since the requirement of back-to-back write for Serial EEPROMs is 10 ms, firmware currently programs this register to
0xA2C2A.
0 Clock Output Tri-state Serial EEPROM clock output tristate control 0 R/W
Table 353: MDI Control Register (Offset 0x6844)
Bit Field Description Init Access
31:4 Reserved – 0 RO
3 MDI Clock When enabled, controls the clock signal at the MDC pin. 0 R/W
2 MDI Select When set, the MDI interface is controlled by this register. 0 R/W
1 MDI Enable When set, the MDI Data Pin is enabled as an output
driver.
0R/W
0 MDI Data When read, returns the value at the MDIO pin. When
written, and the MDI Enable bit is also set, the value is
driven to the MDIO pin.
0R/W
Note: This register is not applicable to the BCM5906 device.
Table 352: Serial EEPROM Control Register (Offset 0x6840) (Cont.)
Bit Field Description Init Access