Broadcom BCM5722 - Table 65: 64-Bit PCI Bus (WSD = 1, BSD = 0); Table 66: 32-Bit PCI Bus (WSD = 1, BSD = 0); Table 67: 64-Bit PCI Bus (WSD = 1, BSD = 1); Table 68: 32-Bit PCI Bus (WSD = 1, BSD = 1)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Endian Control (Byte and Word Swapping) Page 148
Word Swap Data = 1, and Byte Swap Data = 0
Word Swap Data = 1, and Byte Swap Data = 1
So, for a little-endian (e.g., x86) host, software should set both the Word Swap Data, and Byte Swap Data bits. This is
because a little endian host will expect the first byte on the wire (byte D1) to be placed into memory at the least significant
(starting) address of the packet data.
Table 65: 64-Bit PCI Bus (WSD = 1, BSD = 0)
B7 B6 B5 B4 B3 B2 B1 B0
63–56 55–48 47–40 39–32 31–24 23–16 15–8 7–0
D5 D6 S1 S2 D1 D2 D3 D4
T1 T2 IP1 IP2 S3 S4 S5 S6
Table 66: 32-Bit PCI Bus (WSD = 1, BSD = 0)
B3 B2 B1 B0
31–24 23–16 15–8 7–0
D1 D2 D3 D4
D5 D6 S1 S2
S3 S4 S5 S6
T1 T2 IP1 IP2
Table 67: 64-Bit PCI Bus (WSD = 1, BSD = 1)
B7 B6 B5 B4 B3 B2 B1 B0
63–56 55–48 47–40 39–32 31–24 23–16 15–8 7–0
S2 S1 D6 D5 D4 D3 D2 D1
IP2 IP1 T2 T1 S6 S5 S4 S3
Table 68: 32-Bit PCI Bus (WSD = 1, BSD = 1)
B3 B2 B1 B0
31–24 23–16 15–8 7–0
D4 D3 D2 D1
S2 S1 D6 D5
S6 S5 S4 S3
IP2 IP1 T2 T1