Broadcom BCM5722 - Table 271: Receive Data Completion Control Registers; Table 272: Receive Data Completion Mode Register (Offset 0 X2800)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Receive Data Completion Control Registers Page 288
RECEIVE DIAGNOSTIC DATA AND RECEIVE BD RING INITIATOR LOCAL NIC STANDARD
RECEIVE BD CONSUMER INDEX (OFFSET 0X2474)
The NIC local copy of Standard Receive Producer Ring Consumer Index.
RECEIVE DATA AND RECEIVE DIAGNOSTIC BD INITIATOR LOCAL RECEIVE RETURN PRODUCER
INDEX REGISTER
(Offset for BCM5906 Only is 0x2480–0x2483; Offset for all others is 0x2480–0x248F)
These registers are used to keep track of Receive Return Rings 1–4 Producer Indices.
RECEIVE DATA COMPLETION CONTROL REGISTERS
RECEIVE DATA COMPLETION MODE REGISTER (OFFSET 0X2800)
Table 271: Receive Data Completion Control Registers
Offset Registers
0x2800–0x2803 Receive Data Completion Mode
0x2804–0x2bff Reserved
Table 272: Receive Data Completion Mode Register (Offset 0x2800)
Bit Field Description Init Access
31:3 Reserved – 0 RO
2 Attn_Enable When this bit is set to 1, an internal attention is generated
when an error occurs.
0R/W
1 Enable This bit controls whether the Receive Data Completion
state machine is active or not. When set to 0, it completes
the current operation and cleanly halts. Until it is
completely halted, it remains one when read.
1R/W
0 Reset When this bit is set to 1, the Receive Data Completion
state machine is reset. This is a self-clearing bit.
0R/W