BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 223 Message Signaled Interrupts Capabilities Document 5722-PG101-R
MESSAGE ADDRESS REGISTER (OFFSET 0XEC)
This 64-bit register contains the system-specified message address. If the Message Enable bit (bit 0 of the Message Control
Register) is set, the contents of this register specify a 32-bit aligned address for the MSI write transaction.
MESSAGE DATA REGISTER (OFFSET 0XF4)
This 16-bit registers contains a system-specified message. Each MSI function is allocated up to 32 unique messages.
System architecture specifies the number of unique messages supported by the system.
If the Message Enable bit (bit 0 in the Message Control register) is set, the message data is driven onto the lower word of
the memory write transaction’s data phase. The upper 16 bits are driven to zero during the data phase.
The Multiple Message Enable field (bits 6:4 of the Message Control register) defines the number of low-order message data
bits the function is permitted to modify to generate its system software allocated messages. For example, a Multiple Message
Enable encoding of 010 indicates the function has been allocated four messages and is permitted to modify message data
bits 1 and 0 in order to generate up to four unique messages. This field is read/write.
Table 153: Message Address Register (Offset 0xEC)
Bit Field Description Init Access
63:0 MSI Address Register Contains the system-specified message address. X R/W
Table 154: Message Data Register (Offset 0xF4)
Bit Field Description Init Access
15:0 MSI Data Register Contains the system specified message. X R/W
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