Broadcom BCM5722 - Table 240: VLAN Tag Register for TCP Segmentation (Offset 0 Xcf0); Table 241: VLAN Tag Register for TCP Segmentation (Offset 0 Xcf0)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 275 TCP Segmentation Control Registers Document 5722-PG101-R
VLAN TAG REGISTER FOR TCP SEGMENTATION (OFFSET 0XCF0)
PRE-DMA COMMAND EXCHANGE REGISTER FOR TCP SEGMENTATION (OFFSET 0XCF4)
2 Invoke Processor Invoke Processor. Clear the PASS bit of the entry queued
to the SDCQ, so that SDC will invoke the CPU.
• If the packet is created by hardware, this bit will be the
same as bit 9 (BD_FLAG_CPU_POST_DMA) of the
flag field in the Send BD.
• If the packet is created by firmware, it will be up to CPU
whether it needs to post-process the data.
0R/W
1 Don’t Generate CRC Do not Generate CRC. Pass through Send Buffer
Descriptor flag.
0R/W
0 No Byte Swap No Byte Swap. Set to disable endian byte swap on data
from PCI bus.
0R/W
Table 240: VLAN Tag Register for TCP Segmentation (Offset 0xCF0)
Bit Field Description Init Access
31:16 Reserved – 0 RO
15:0 VLAN Tag VLAN tag to be inserted into the Frame Header if bit 7 of
DMA Flags register is set.
0R/W
Table 241: VLAN Tag Register for TCP Segmentation (Offset 0xCF0)
Bit Field Description Init Access
31 READY The CPU sets this bit to tell the SDI that the DMA
address, length, flags, and VLAN tag are valid and the
request is ready to be go. The CPU polls this bit to be
clear for the completion of the request.
0R/W
30 PASS If this bit is set to 0, the CPU will be responsible for
processing the buffer descriptor.
1R/W
29 SKIP The CPU sets this bit to 1 to inform the SDI that the TCP
segmentation is completed, and the BD_Index can be
incremented.
0R/W
28:7 Reserved – 0 RO
6:0 BD_Index The internal current buffer descriptor pointer that the
hardware/firmware is servicing.
0R/W
Table 239: DMA Flags Register for TCP Segmentation (Offset 0xCEC) (Cont.)
Bit Field Description Init Access