Broadcom BCM5722 - Figure 61: WOL Functional Block Diagram

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 159 Wake on LAN Mode/Low-Power Document 5722-PG101-R
• PHY auto-negotiation
• BCM5722 Ethernet controller power management
FUNCTIONAL OVERVIEW
The BCM5722 Ethernet controller is capable of WOL in 10/100 Mbps for copper-based controllers.
The BCM5722 Ethernet controller uses the TX FIFO to store pattern data (see Figure 61). During WOL operation, the
transmit engine is disabled and its FIFO is free for use. The TDE fetches data from the memory arbiter starting at a location
specified in the WOL_Pattern_Pointer register. The WOL pattern checker pulls data off the TX FIFO for packet comparisons.
The RX MAC will move incoming frame(s) to the pattern checker, and the remaining RX data path is not utilized. A state
machine controls the Magic Packet comparisons. The WOL state machine will move out of an Idle state, when ACPI power
management is enabled. The WOL state machine will clear the TX FIFO and Match register. The Match register indicates a
positive Magic Packet comparison(s) on a stream.
In 10/100 Mbit mode, data is received once every four clock cycles. The pattern checker compares the first three patterns
in the first cycle, the second three patterns in the second cycle, and the third three patterns in the last cycle. It is idle during
the fourth cycle. In gigabit mode, the pattern checker gets three pattern words from the FIFO at one time.
Figure 61: WOL Functional Block Diagram
Note: When configured for WOL in 1000-Mbps mode, the BCM5722 Ethernet controller draws more than the 375
mA allowed by the PCI specification.
Rx MAC
Pattern
Checker
Tx FIFO TDE
Memory
Arbiter
Internal
Memory
Pattern
Data
RX
PCS
RX
RMII
RX
GMII
RX
IO
Power
Managment