Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Wake on LAN Mode/Low-Power Page 158
12. Enable Flow Control (see “Flow Control” on page 170).
13. Configure MAC port mode. The driver state variables from Step 11. are used to configure the Port_Mode bit field in the
Ethernet MAC Mode register (see “Ethernet MAC Mode Register (Offset 0x400)” on page 245). This step should be
completed each time link changes—the port mode does not reflect the type of PHY attached to the MAC, rather
Port_Mode configures the hardware interface between MAC and PHY.
14. Configure duplex mode. The driver state variables from Step 11. are used to configure the Half_Duplex bit in the Ethernet
MAC Mode register (see “Ethernet MAC Mode Register (Offset 0x400)” on page 245).
15. Configure how MAC determines the PHY Link Status. Software should set the Port_Polling bit in the MI_Mode register
(see “MI Mode Register (Offset 0x454)” on page 252) for Auto Polling Mode.
16. Enable link attentions. Software should enable link attentions, so a host line interrupt is driven when link state changes.
Programmers may choose the type of attentions generated with the Ethernet MAC Event Enable register (see “Ethernet
MAC Event Enable Register (Offset 0x408)” on page 247):
• PHY interrupt attentions are enabled by asserting the MI_Interrupt bit.
• Port polling attentions are enabled by asserting the Link_State_Changed bit.
• LNKRDY attentions are also enabled by asserting the Link_State_Changed bit.
WAKE ON LAN MODE/LOW-POWER
DESCRIPTION
The BCM5722 Ethernet controller uses the ACPI D3 hot/cold (low-power) state to conserve energy. The OS power manage-
ment policy notifies device drivers to initiate power management transitions. The device driver should move the MAC into
the D3 hot/cold power state—a response to the power management request (see Appendix B ”PC Power Management” on
page 518 for more details on power management). While the BCM5722 Ethernet controller is in a D3 state, the RX MAC will
filter incoming packets. The RX MAC compares incoming traffic for Interesting Packet pattern matches. The BCM5722 Ether-
net controller asserts the PCI PME
signal, when a positive WOL packet comparison is made. The PME signal notifies the
Operating System and host device driver to transition the MAC into the D0 (high power) state.
WOL mode is a combination of PHY and MAC configurations. Both the PHY and MAC must be configured correctly to enable
Broadcom’s WOL technology. The BCM5722 Ethernet controller provides WOL pattern filters for 10/100 wire speeds.
The BCM5722 Ethernet controller supports both Interesting Packet pattern matching the AMD Magic Packet proprietary
technology for WOL. The WOL support for the AMD Magic Packet format does not require host software to configure a pat-
tern filter. The Magic Packet comparison is made in hardware and is enabled through a register interface. The AMD Magic
Packet can be either broadcast or directed, and must contain the receiver's MAC address at least six times (repeating) in
the packet. The Magic Packet wake-up is configured different from pattern match wake-up.
The following components are involved in WOL operation:
• Internal memory
• WOL Pattern Pointer register
• WOL Pattern Configuration register
• WOL streams
• Pattern data structure
• GPIO
• Firmware mailbox
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