Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Flow Control Page 170
15. Set the RX RISC_Clock_Disable bit in the PCI Clock_Control register (see “PMCSR-BSE Register (Offset 0x4E)” on
page 198). The receive CPU will be stopped, and the clocking circuitry disabled.
16. Set the Enable_Alternate_Clock bit in the PCI Clock_Control register (see “PCI Clock Control Register (Offset 0x74)” on
page 207). The BCM5722 Ethernet controller’s 133-MHz Phase Locked Loop (PLL) no longer clocks internal logic and
an alternate clock reference is used. Set the PLL LowPowerClock bit while keeping the Enable_Alternate_Clock bit set.
Wait at least 27 µs and then clear the Enable_Alternate_Clock bit. The BCM5722 Ethernet controller’s PLL is then
switched to its lower power consumption mode.
17. In NIC applications, switch from VMAIN to VAUX in order to prevent a GRC reset. Set the required GPIOs of BCM5722
Ethernet controller if any of them are used for switching the power from VMAIN to VAUX.
18. Enable the RX MAC by setting the Enable bit of “Receive MAC Mode Register (Offset 0x468)” on page 254” and put it
in promiscuous mode by setting the Promiscuous Mode bit of “Receive MAC Mode Register (Offset 0x468)” on page 254.
19. Enable the PME bit in the PCI “PMCSR-BSE Register (Offset 0x4E)” on page 198. The BCM5722 Ethernet controller
asserts PME to wake up the system. Set the Power_State bits to D3 in the “PMCSR-BSE Register (Offset 0x4E)” on
page 198.
FLOW CONTROL
DESCRIPTION
The BCM5722 Ethernet controller supports IEEE 802.3x flow control. Flow control is a switched Ethernet capability, where
link partners may pause traffic. The 802.3x flow control specifies that a MAC sublayer may transmit pause frames. The pause
frames instruct the MAC’s link partner to wait a specified amount of time, before sending additional frames. This delay
provides the MAC time to free packet buffers. Conversely, the MAC sublayer must also accept/receive pause frames. Flow
control is used by switches and bridges to prevent clients of dissimilar speeds from exhausting switching packet buffers.
Clients and servers may use flow control for similar reasons. A very important requirement is that both link partners must
share a full-duplex connection for flow control to be enabled. IEEE 802.3x flow control does not operate on a half-duplex
connection. More information on flow control can be found in Appendix A ”Flow Control” on page 513.
The following architectural blocks are integral to flow control:
• Transmit MAC
• Receive MAC
• Statistics Block
• PHY Auto-negotiation
• PHY Auto-Advertise
OPERATIONAL CHARACTERISTICS
The BCM5722 Ethernet controller implements pause functionality using Xon and Xoff states. The MAC will extract a pause
quantum from a pause control frame. Then, the MAC will configure its internal timer with the pause_time specified by the
link partner. Frames that are currently in the transmit engine will be completed before the transmit engine is inhibited. The
MAC has moved flow control into a Xoff state once the transmit engine is inhibited. Note that the transmit engine is not
completely disabled since the IEEE 802.3 specification stipulates that MAC control frames should not be paused.
One of the following conditions moves the BCM5722 Ethernet controller into an Xon state:
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