BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 481 Transceiver Registers (BCM5906/BCM5906M) Document 5722-PG101-R
TRANSCEIVER REGISTERS (BCM5906/BCM5906M)
This section describes the MII registers of the integrated 10/100 PHY transceivers. The access to the transceiver registers
is provided indirectly through the MII Communication Register (see “MI Communication Register (Offset 0x44C)” on
page 251) of the MAC. The transceiver registers are accessed with the PHY_Addr bit of the MII Communication Register
set to 0x1.
MII MANAGEMENT INTERFACE REGISTER PROGRAMMING
The PHY core fully complies with the IEEE 802.3u Media Independent Interface (MII) specification. The MII management
interface registers of each port are serially written-to and read-from using a common set of MDIO and MDC pins. A single
clock waveform must be provided to the PHY ore at a rate of 0–25 MHz through the MDC pin. The serial data is
communicated on the MDIO pin. Every MDIO bit must have the same period as the MDC clock. The MDIO bits are latched
on the rising edge of the MDC clock. Every MII read or write instruction frame contains the following fields:
Preamble (PRE). Thirty-two consecutive 1 bits must be sent through the MDIO pin to the PHY core to signal the beginning
of an MII instruction. Fewer than 32 1 bits causes the remainder of the instruction to be ignored.
Start of frame (ST). A 01 pattern indicates that the start of the instruction follows.
Opcode (OP). A read instruction is indicated by 10, while a write instruction is indicated by 01.
PHY address (PHYAD). A 5-bit PHY address follows next, with the MSB transmitted first. The PHY address allows a single
MDIO bus to access multiple PHY chips. The PHY core supports a complete address space with PHYAD[4:0] input pins
used as the base address for selecting one of the eight transceivers.
Register address (REGAD). A 5-bit register address follows, with the MSB transmitted first.
Turnaround (TA). The next two bit times are used to avoid contention on the MDIO pin when a read operation is performed.
For a write operation, 10 must be sent to the PHY core chip during these two bit times. For a read operation, the MDIO pin
must be placed into High-Impedance during these two bit times. The chip drives the MDIO pin to 0 during the second bit time.
DATA. The last 16 bits of the frame are the actual data bits. For a write operation, these bits are sent to the PHY, whereas,
for a read operation, these bits are driven by the PHY. In either case, the MSB is transmitted first. When writing to the PHY,
the data field bits must be stable 10 ns before the rising-edge of MDC, and must be held valid for 10 nanoseconds after the
rising edge of MDC. When reading from the PHY, the data field bits are valid after the rising-edge of MDC until the next
rising-edge of MDC.
Idle. A high-impedance state of the MDIO line. All tri-state drivers are disabled and the pull-up resistor of the PHY pulls the
MDIO line to logic 1. Note that at least one or more idle states are required between frames.
Following are two examples of MII write and read instructions.
Table 536: MII Management Frame Format
Operation PRE ST OP PHYAD REGAD TA DATA Idle Direction
READ 1 ... 1 01 10 AAAAA RRRRR ZZ
Z0
Z ... Z
D ... D
ZZ Driven to PHY core
Driven by PHY core
WRITE 1 ... 1 01 01 AAAAA RRRRR 10 D ... D Z Driven to PHY core
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