Broadcom BCM5722 - Table 155: Advanced Error Reporting Enhanced Capability Header Register (Offset 0 X100); Table 156: Uncorrectable Error Status Register (Offset 0 X104)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R PCIe-Enhanced Capabilities Page 224
PCIE-ENHANCED CAPABILITIES
PCIe devices may optionally support a new configuration space that provides an additional 4 KB of configuration registers
per device. This enhanced configuration space is mapped into host memory through a 256 MB window (enabled through the
Root Complex) that provides access to the 4-KB enhanced configuration space for each of the 64K possible PCIe devices.
Refer to the PCIe specification for additional details on how to access the enhanced configuration space.
The offsets listed for the following registers indicate the offset from the beginning of the enhanced configuration space for
that device.
ADVANCED ERROR REPORTING ENHANCED CAPABILITY HEADER REGISTER (OFFSET 0X100)
UNCORRECTABLE ERROR STATUS REGISTER (OFFSET 0X104)
Table 155: Advanced Error Reporting Enhanced Capability Header Register (Offset 0x100)
Bit Field Description Init Access
31:20 Next Capability Offset Pointer to the Virtual Channel Capability Structure 0x13C RO
19:16 Capability Version This value indicates the version of this enhanced capability
header.
1RO
15:0 Extended Capability ID This value indicates the type of enhanced capability
header for this block and is hard-wired to one to indicate
the Advanced Error Reporting capability.
1RO
Table 156: Uncorrectable Error Status Register (Offset 0x104)
Bit Field Description Init Access
31:21 Reserved – 0 RO
20 Unsupported Request
Error Status
This bit is set when an Unsupported Request Error occurs. 0 W2C
19 ECRC Error Status This bit is set when an ECRC error occurs. 0 W2C
18 Malformed TLP Status This bit is set when a Malformed TLP error occurs. 0 W2C
17 Receiver Overflow
Status
This bit is set when a Receiver Overflow error occurs. 0 W2C
16 Unexpected
Completion Status
This bit is set when an Unexpected Completion error
occurs.
0W2C
15 Completer Abort Status This bit is set when a Completer Abort error occurs. 0 W2C
14 Completion Timeout
Status
This bit is set when a Completion Timeout error occurs. 0 W2C
13 Flow Control Protocol
Error Status
This bit is set when a Flow Control Protocol error occurs. 0 W2C
12 Poisoned TLP Status This bit is set when a Poisoned TLP error occurs. 0 W2C
11:5 Reserved – 0 RO
4 Data Link Protocol
Error Status
This bit is set when a Data Link Protocol error occurs. 0 W2C
3:1 Reserved – 0 RO
0 Training Error Status This bit is set when a Training error occurs. 0 W2C