Broadcom BCM5722 - Figure 54: Read and Write Channels of DMA Engine

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 133 Bus Interface Document 5722-PG101-R
Register Read Using Indirect Mode
PCI_CFG_WRITE(Register_Base_Address, BCM57XXXRegAddr)
Value = PCI_CFG_READ(Register_Data_Register)
Register Write Using Indirect Mode
PCI_CFG_WRITE(Register_Base_Address, BCM57XXXRegAddr)
PCI_CFG_WRITE(Register_Data_Register, Value)
BUS INTERFACE
DESCRIPTION
The read/write DMA engines both drive the PCIe interface. Normally, each DMA engine alternates bursts to the PCIe bus,
and both interfaces may have outstanding transactions on the PCI bus. The BCM5722 architecture identifies two
channels—a read DMA channel and a write DMA channel. Each channel corresponds to the appropriate DMA engine (see
Figure 54). The configuration of the DMA engines and the PCI interface is discussed in this section.
Figure 54: Read and Write Channels of DMA Engine
PCI Interface
Write FIFO Read FIFO
DMA Write
Engine
DMA Read
Engine
Write Chann
elR
ead Channel
PCIe Bus