Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Bus Interface Page 134
The following architectural components are involved in the configuration of the PCI/DMA interface:
• DMA read engine
• DMA write engine
• DMA read FIFO
• DMA write FIFO
• PCIe interface
• PCI state register
• DMA read/write register
OPERATIONAL CHARACTERISTICS
Read/Write DMA Engines
Software must enable the bus master DMA bit for the BCM5722 Ethernet controller. The BCM5722 Ethernet controller is a
bus-mastering device and the PCI interface requires that the Bus_Master enable bit be set by either the BIOS or host device
driver. The bus master is the PCI transaction initiator. A PCI target will claim the transaction driven by the bus master. The
Bus_Master enable bit is located in the PCI configuration space Command register (see “Command Register (Offset 0x04)”
on page 190) and this bit is read/write. The bit defaults to cleared/disabled after device reset.
The read and write DMA channels use FIFOs to buffer small amounts of PCI bus data. The FIFOs provide elasticity for data
movement between internal memory and the PCI interface. Host software may configure DMA watermarks—values where
PCI activity is enabled/disabled.
When enqueued data is less than the watermark value, PCI bus transactions are inhibited. The DMA channel will wait until
the FIFO fills above the threshold before initiating PCI transactions. Host software may configure the
DMA_Write_Watermark bit fields to set the activity threshold in the write FIFO. The DMA_Write_Watermark bit field is read/
write and is also located in the DMA Read/Write register. The write watermark registers default to zero after power-on reset.
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