Broadcom BCM5722 - Table 474: PHY Timing Parameter Override Register (Offset 0 X7 E34); Table 475: PHY Hardware Diagnostic 1 Register (Offset 0 X7 E38)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R PCIe Registers Page 412
PHY TIMING PARAMETER OVERRIDE REGISTER (OFFSET 0X7E34)
PHY HARDWARE DIAGNOSTIC 1 REGISTER (OFFSET 0X7E38)
Table 474: PHY Timing Parameter Override Register (Offset 0x7E34)
Bit Field Description Init Access
31 ts1NumOverride Set to override the TS1 number to be sen out in polling active state
with the value in bit (27:16) of this register from the specification
defined value.
0R/W
30 txIdleMinOverride Set to override the min time for a transmitter to stay with the value in
bit (15:8) of this register from the specification defined value.
0R/W
29 txIdle2IdleOverride Set to override the Max time for electrical idle transition with the value
in bit (7:0) of this register from the specification defined value.
0R/W
28 Reserved – 0 RO
27:16 N_TS1InPollingActive TS1 number needed to be sent in Polling active state. 0x400 R/W
15:8 txIdleMinTime Minimum time (in symbol time) a transmitter must be in electrical idle. 0x5 R/W
7:0 txIdleSettoIdleTime Maximum time (in symbol time) to transition to a valid electrical idle
after sending an electrical idle ordered-set.
0x2 R/W
Table 475: PHY Hardware Diagnostic 1 Register (Offset 0x7E38)
Bit Field Description Init Access
31:10 Reserved – 0 RO
9:4 Transmit State
Machine State
Transmit state machine states:
• 9:8 = TX Data State
• 7:4 = TX Main State
0RO
3:0 Receive State Machine
State
Receive state machine states 3:0 = RX Main State 0 RO