Broadcom BCM5722 - Table 325: Virtual CPU Debug Register Fields (Offset 0 X5110); Table 326: Virtual CPU Debug Register Fields (Offset 0 X5110); Table 327: Virtual CPU Debug Register Fields (Offset 0 X5110); Virtual CPU Debug Register (Offset 0 X5110)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 323 Virtual CPU Registers (BCM5906 Only) Document 5722-PG101-R
VIRTUAL CPU DEBUG REGISTER (OFFSET 0X5110)
VIRTUAL CPU SHADOW 1 REGISTER (OFFSET 0X5114)
VIRTUAL CPU SHADOW 2 REGISTER (OFFSET 0X5118)
Table 325: Virtual CPU Debug Register Fields (Offset 0x5110)
Bit Field Description Init Access
31:13 Reserved – 0 R/O
12:10 Irom_St[2:0] The state of the internal ROM image loading FSM 0 R/O
9:6 Erom_St[3:0] The state of the external EEPROM image loading FSM 0 R/O
5:0 Vcpu_St[5:0] The state of the VCPU main FSM 0 R/O
Table 326: Virtual CPU Debug Register Fields (Offset 0x5110)
Bit Field Description Init Access
31:0 MBA configuration
register
The VCPU reads the MBA configuration data from external
EEPROM.
0R/W
Table 327: Virtual CPU Debug Register Fields (Offset 0x5110)
Bit Field Description Init Access
31:24 Reserved – 0 R/W
23:0 MBA misc
configuration register
The VCPU reads the MBA misc configuration data from external
EEPROM.
0R/W