Broadcom BCM5722 - Integrated Phys; PHY Auto-Negotiation; Register Quick Cross Reference; Table 89: PHY Flow Control Registers

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 173 Flow Control Document 5722-PG101-R
PHY Auto-Negotiation
The PHY encodes flow control capability into Fast Link Pulse (FLPs) bursts. Link partners will extract encoded flow control
capability from FLPs and then create a Link Code Word (LCW). The LCW is a message, which contains a selector and
technology ability field. The technology ability field contains a bit called Pause_Operation_for Full_Duplex_Link (A5). Refer
to Annex 28-B of the IEEE 802.3 specifications. The A5 bit signifies that a link partner has implemented pause functionality.
If both link partners support auto-negotiation, they will further exchange data regarding flow control, using the next page bit
in the LCW.
Auto-advertise is integrally tied to auto-negotiation. If link partner does not support pause functionality, the PHY
Auto_Negotation_Link_Partner_Ability_Register does not set the Pause_Capable bit. The BCM5722 Ethernet controller
should not send pause frames to this link partner since flow control is not implemented or disabled. The BCM5722 Ethernet
controller can still accept pause frames, but sending a pause frame does not yield a preferred result.
REGISTER QUICK CROSS REFERENCE
Integrated PHYs
Table 89 lists the flow control registers in the integrated PHYs.
Table 89: PHY Flow Control Registers
MDI Register Bit(s) Name Description Cross Reference
MII_status Link_Status Link Pass State which indicates if a
valid link has been established.
“MII Status Register (PHY_Addr =
0x1, Reg_Addr = 01h)” on
page 416.
MII_auxiliary_status Auto_Negotation_HCD Current operating mode and speed “Auxiliary Status Summary
Register (PHY_Addr = 0x1,
Reg_Addr = 19h)” on page 450.
Auto-negotiation
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Asymetric_Pause Advertise to link partner, that
asymmetric pause is desired. This bit
works in conjunction with
Pause_Capable bit.
“Auto-Negotiation Advertisement
Register (PHY_Addr = 0x1,
Reg_Addr = 04h)” on page 419.
Pause_Capable The pause capable bit indicates
whether half/full-duplex pause is
advertised.
Auto-negotiation Link
Partner Ability
Asymetric_Pause Link Partner capability—the partner
desires asymmetric pause.
“Auto-Negotiation Link Partner
Ability Register (PHY_Addr = 0x1,
Reg_Addr = 05h)” on page 421.
Pause_Capable Link partner capability—the partner is
capable of full or half-duplex pause.