Broadcom BCM5722 - Read DMA Programmable Ipv6 Extension Header Register (Offset: 0 X4808); Read DMA Status Register (Offset 0 X4804); Table 310: Read DMA Status Register (Offset 0 X4804); Table 311: Read DMA Programmable Ipv6 Extension Header Register (Offset: 0 X4808)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 313 Read DMA Control Registers Document 5722-PG101-R
READ DMA STATUS REGISTER (OFFSET 0X4804)
READ DMA PROGRAMMABLE IPV6 EXTENSION HEADER REGISTER (OFFSET: 0X4808)
Table 310: Read DMA Status Register (Offset 0x4804)
Bit Field Description Init Access
31:11 Reserved – 0 RO
10 Read DMA PCI-X Split Transaction
Timeout Expired
Read DMA PCI-X split transaction timeout expired. 0 W2C
9 Read DMA Local Memory Write
Longer Than DMA Length Error
Read DMA Local Memory Write Longer Than DMA Length
Error.
0W2C
8 Read DMA PCI FIFO Overread Error Read DMA PCI FIFO Overread Error (PCI read longer
than DMA length).
0W2C
7 Read DMA PCI FIFO Underrun Error Read DMA PCI FIFO Underrun Error. 0 W2C
6 Read DMA PCI FIFO Overrun Error Read DMA PCI FIFO Overrun Error. 0 W2C
5 Read DMA PCI Host Address
Overflow Error
Read DMA PCI Host Address Overflow Error. A host
address overflow occurs when a single DMA read begins
at an address below a multiple of 4 GB and ends at an
address above the same multiple of 4 GB (i.e., the host
memory address transitions from
0xXXXXXXXX_FFFFFFFF to 0xYYYYYYYY_00000000
in a single read). This is a fatal error.
0W2C
4 Read DMA PCI Parity Error Read DMA PCI Parity Error. 0 W2C
3 Read DMA PCI Master Abort Error Read DMA PCI Master Abort Error. 0 W2C
2 Read DMA PCI Target Abort Error Read DMA PCI Target Abort Error. 0 W2C
1:0 Reserved – 0 W2C
Note: This register is not applicable to the BCM5906 device.
Table 311: Read DMA Programmable IPv6 Extension Header Register (Offset: 0x4808)
Bit Field Description Init Access
31 Programmable Extension Header
Type #2 Enable
This bit enables programmable extension header #2. If
this bit is clear, then the value programmed in bits [15:8] of
this register will be ignored. If this bit is set, then extension
headers will be checked for a type matching the value in
bits [15:8].
0R/W
30 Programmable Extension Header
Type #1 Enable
This bit enables programmable extension header #1. If
this bit is clear, then the value programmed in bits [7:0] of
this register will be ignored. If this bit is set, then extension
headers will be checked for a type matching the value in
bits [7:0].
0R/W
29:16 Reserved Reserved bits 0 RO
15:8 Programmable Extension Header
Type #2
These bits contain the programmable extension header
value for programmable header #2.
0R/W
7:0 Programmable Extension Header
Type #1
These bits contain the programmable extension header
value for programmable header #1.
0R/W