Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Read DMA Control Registers Page 312
25 Address Overflow Error Logging
Enable
This bit when set, enables the address overflow error to
be generated when the DMA Read Engine performs a
DMA operation that crosses a 4G boundary. This error is
reported in bit 3 of the DMA Read Status Register.
Subsequently, this will generate an internal event to
interrupt the internal CPU and the DMA Read Engine will
lock up after detecting this error. So it’s recommended
that this bit should not be set by firmware or software.
• 1 = Enable Address Overflow Error Logging
• 0 = Disable Address Overflow Error Logging.
0R/W
24:18 Reserved – 0 RO
17:16 PCI Request Burst Length The two bits define the burst length that the RDMA read
engine would request to the PCI block.
• 00 = 128 bytes
• 01 = 256 bytes
• 10 = 512 bytes
• 11 = 4 KB if core clock is not slowed down to 6.25 MHz
• 11 = 256 bytes if core clock is slowed down to
6.25 MHz
0R/W
Reserved (BCM5906 only) – 0 RO
15:11 Reserved – 0 RO
10 Read DMA PCI-X Split Transaction
Timeout Expired Attention Enable
Enable read DMA PCI-X split transaction timeout expired
attention.
0R/W
9 Read DMA Local Memory Write
Longer Than DMA Length Attention
Enable
Enable Read DMA Local Memory Write Longer Than
DMA Length Attention.
0R/W
8 Read DMA PCI FIFO Overread
Attention Enable
Enable Read DMA PCI FIFO Overread Attention (PCI
read longer than DMA length.)
0R/W
7 Read DMA PCI FIFO Underrun
Attention Enable
Enable Read DMA PCI FIFO Underrun Attention. 0 R/W
6 Read DMA PCI FIFO Overrun
Attention Enable
Enable Read DMA PCI FIFO Overrun Attention. 0 R/W
5 Read DMA PCI Host Address
Overflow Error Attention Enable
Enable Read DMA PCI Host Address Overflow Error
Attention. A host address overflow occurs when a single
DMA read begins at an address below 4 GB and ends on
an address above 4 GB. This is a fatal error.
0R/W
4 Read DMA PCI Parity Error
Attention Enable
Enable Read DMA PCI Parity Error Attention. 0 R/W
3 Read DMA PCI Master Abort
Attention Enable
Enable Read DMA PCI Master Abort Attention. 0 R/W
2 Read DMA PCI Target Abort
Attention Enable
Enable Read DMA PCI Target Abort Attention. 0 R/W
1 Enable This bit controls whether the Read DMA state machine is
active or not. When set to 0, it completes the current
operation and cleanly halts. Until it is completely halted, it
remains one when read.
1R/W
0 Reset When this bit is set to 1, the Read DMA state machine is
reset. This is a self-clearing bit.
0R/W
Table 309: Read DMA Mode Register (Offset 0x4800) (Cont.)
Bit Field Description Init Access
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