Broadcom BCM5722 - Table 175: Power Budgeting Data Register (Offset 0 X174); Table 176: Power Budgeting Capability Register (Offset 0 X178)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R PCIe-Enhanced Capabilities Page 232
POWER BUDGETING DATA REGISTER (OFFSET 0X174)
POWER BUDGETING CAPABILITY REGISTER (OFFSET 0X178)
Table 175: Power Budgeting Data Register (Offset 0x174)
Bit Field Description Init Access
31:21 Reserved – 0x0 RO
20:18 Power Rail Specifies the power rail of the operating condition
12V (000)
3.3V (001)
1.8V (010)
Thermal (111) (Not supported)
000 RW from Internal CPU
Config RO
Memory RW
Bit-20 is hard-wired to
zero and hence is RO
17:15 Type Specifies the type of the operating condition
PME Aux (000)
Auxiliary (001)
Idle (010)
Sustained (010)
Maximum (111)
000 RW from Internal CPU
Config RO
Memory RW
14:13 PM State Specifies the power management state of operating
condition—D0, D3
00 RW from Internal CPU
Config RO
Memory RW
12:10 PM Sub State Specifies the sub states of the operating condition 000 RO
9:8 Data Scale Specifies the scale to apply to the base power value—0x1 for
0.1x scale. This value depends on the PCIe Data Select value
and the Data Select Limit (bits 15:12 of 0x7C04). This field will
be zero if the PCIe Data Select is greater than the Data Select
Limit.
0x0 RW from Internal CPU
Config RO
Memory RW
7:0 Base Power Specifies in Watts the base power value in given operating
conditions. This value depends on the Data Select Register
and the programmable firmware registers in offset
0x17C–0x18B.
0x00 RW from Internal CPU
Config RO
Memory RW
Table 176: Power Budgeting Capability Register (Offset 0x178)
Bit Field Description Init Access
31:1 reserved 0x000000 RO
0 LOM Configuration Indicate that the power budget for the device is
included within the system power budget
Derived from NVRAM configuration
If Configured as LOM, then write 1 to bit 5 of 0x7C04
else write 0
0 RW from Internal CPU
Config RO
Memory RW