Broadcom BCM5722 - Table 364: Energy Detect Timer Register (Offset: 0 X689 C)

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Wake-on-LAN Registers Page 350
ENERGY DETECT TIMER REGISTER (OFFSET: 0X689C)
This register is used to debounce the raw energy_det signal from the EPHY core.
Note: This register is applicable to BCM5755, BCM5755M, BCM5906, BCM5906M only.
In BCM5755 and BCM5755M, this register is used as part of CableSense feature.
Table 364: Energy Detect Timer Register (Offset: 0x689C)
Bit Field Description Init Access
31 Fast_timer_mode • 1 = Directly use timers in this register without multiplying by
2
11
x 2
9.
It is mainly used for simulation purposes.
• 0 = Normal mode
0 RW
30:24 Reserved Reserved bits 0 RO
23:16 short_timer[7:0] The timer used for Pending_ON state of Energy_Det FSM. If
energy is seen for a period of short_timer, FSM goes to
FULL_ON state. The time is calculated as:
2
11
x short_timer x 40 ns
The default time is 1.311 ms. This bit is reset by hard_reset
only.
0x10 R/W
15:8 long_timer[7:0] The timer used for Pending_ON state of Energy_Det FSM. If
no energy is seen for a period of long_timer, FSM goes to
FULL_OFF state. The time is calculated as:
2
11
x 2
9
x long_timer x 40 ns
The default time is 1.342s. This bit is reset by hard_reset only.
0x20 R/W
7:0 longer_timer[7:0] The timer used for Pending_OFF state of Energy_Det FSM. If
no energy is seen for a period of longer_timer, FSM goes to
FULL_OFF state. The time is calculated as:
2
11
x 2
9
x longer_timer x 40 ns
The default time is 2.684s. When FSM is in FULL_ON or
Pending_OFF state, Energy_Det output pin is asserted.
This bit is reset by hard_reset only.
0x40 R/W