Broadcom BCM5722 - Table 413: TLP Control Register (Offset 0 X7 C00)

BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 383 PCIe Registers Document 5722-PG101-R
TLP CONTROL REGISTER (OFFSET 0X7C00)
0x7E20 PHY Receive Error Counter
0x7E24 PHY Receive Framing Error Counter
0x7E28 PHY Receive Error Threshold register
0x7E2C PHY Test Control register
0x7E30 PHY/SerDes Control Override
0x7E34 PHY Timing Parameter Override
0x7E38 PHY Hardware Diagnostic1 n TX/RX SM States
0x7E3C PHY Hardware Diagnostic2 n LTSSM States
Table 413: TLP Control Register (Offset 0x7C00)
Bit Field Description Init Access
31 Enable Excessive current Fix
(CQ10362 Fix).
Enable the DOS excessive current fix:
• 0 = Disable fix
• 1 = Enable fix
1R/W
30 Reserved – 0 RO
29 Enable Interrupt Mode Fix (CQ
9804 Fix)
Enable the Interrupt Mode Fix:
• 0 = Disable fix
• 1 = Enable fix
1R/W
28 Reserved – 0 RO
27 Enable Unexpected
Completion Error Fix (CQ
9321 Fix)
Enable the Unexpected Completion Error Fix:
• 0 = Disable fix
• 1 = Enable fix
The hardware fix is to not send the Unexpected Completion Error
message when the chipset replays a completion packet because
of BIOS not programming the chipset’s replay timer correctly.
1R/W
26 Enable Type1 Vendor Defined
Message Fix (CQ 9583)
Enable the Type 1 Vendor Defined Message Fix:
• 0 = Disable fix
• 1 = Enable fix
The fix for this is to discard any Type1 message with a data
payload of two or more DWs to prevent the data FIFO from getting
out of sync.
0R/W
25 Data FIFO Protect When set, this bit enables Data FIFO protection. 0 R/W
24 Enable Address Check When set, this bit enables Address and Type field checking in the
Transaction Layer Packet (TLP).
1R/W
23 Enable TC0 Check When set, this bit enabled TC0 Traffic Class checking in the TLP. 1 R/W
22 CRC Swap When set, this bit enables swapping of the digest field when
ECRC is enabled.
0R/W
21 Disable CA Error When clear, this bit enables the DMA completion logic to check
for a completion packet with a Completer Abort Completion
Status value.
0R/W
Table 412: PCIe Registers (Cont.)
Address Description