Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Transceiver Registers (BCM5906/BCM5906M) Page 496
100BASE-X False Carrier Sense Counter
Overrun/Underrun Counter [7:0]
The overrun/underrun counter increments each time the PHY detects an overrun or underrun of the receive FIFOs. The
counter automatically clears itself when read. When the counter reaches its maximum value, FFh, it stops counting overrun/
underrun errors until cleared.
False Carrier Sense Counter [7:0]
This counter increments each time the PHY detects a false carrier on the receive input. This counter automatically clears
itself when read. When the counter reaches its maximum value, FFh, it stops counting false carrier sense errors until cleared.
100BASE-X Disconnect Counter
SMII Fast RXD
Extended FIFO operation only. Bit 15 of the Disconnect Counter register indicates the FIFO state machine has detected fast
receive data relative to the reference input.
SMII Slow RXD
Extended FIFO operation only. Bit 14 of the Disconnect Counter register indicates the FIFO state machine has detected slow
receive data relative to the reference input.
Table 549: 100BASE-X False Carrier Sense Counter (Address 19d, 13h)
Bit Name R/W Description Default
15:8 SMII Overrun/Underrun
Counter [7:0]
R/W Number of overruns/underruns since last read 00h
7:0 False Carrier Sense
Counter [7:0]
R/W Number of false carrier sense events since last read 00h
Table 550: 100BASE-X Disconnect Counter (Address 20d, 14h)
Bit Name R/W Description Default
15 SMII Fast RXD R/O 1 = In extended FIFO mode, detect fast receive data
0 = Normal
0
14 SMII Slow RXD R/O 0 = Normal
1 = In extended FIFO mode, detect slow receive data
0
13:8 Reserved - - 000010
7:0 Reserved - - 00h
R/W = Read/Write, RO = Read only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL and LH Clear after read
operation. Use default values of reserved bit(s) when writing to reserved bit(s).
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