BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 457 Transceiver Registers Document 5722-PG101-R
SPARE CONTROL 2 (PHY_ADDR = 0X1, REG_ADDR = 1CH, SHADOW 00100B)
Write Enable
During a write to this register, setting Spare Control 2 Register bit 15 allows writing to bits [9:0] of this register. For reading
the values of bits [9:0], perform an MDIO write with bit 15 cleared and preferred shadow values in bits [14:10]. The next MDIO
read of register address 1Ch contains the preferred Shadow register values in bits [9:0].
Shadow Register Selector
Bits [14:10] must be set to 00100 to enable read/write to the Spare Control 2 register.
Energy Detect on INTR Pin
Setting bit one of this register enables the Energy Detect function on the INTR pin. Otherwise, the INTR pin defaults to
Interrupt function.
Table 518: Spare Control 2 Register (Address 1Ch, Shadow Value 00100)
Bit Field Description Init Access
15 Write Enable • 1 = Write bits [9:0].
• 0 = Read bits [9:0].
0R/W
14:10 Shadow Register Selector 00100 = Spare Control 2 register. 00100 R/W
9:5 Reserved Write as 00h, ignore when read. 00h RO
4:2 Reserved Write as 011, ignore when read. 011 RO
1 Energy Detect on INTR pin
• 1 = routes Energy Detect to interrupt signal. Use LED
selectors (reg 1Ch shadow 01101 and 01110) and
program to INTR mode.
• 0 = INTR pin is Interrupt function.
0R/W
0 Reserved Write as 0, ignore when read. 0 RO
To Next Page
Loading...