Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Configuration Space Page 108
Two programmable blocks expose BCM5722 Ethernet controller functionality to host software. The first is a register block.
The second is a memory block. The register and memory blocks map into address spaces based on processor context. For
example, the BCM5722 Ethernet controller has an on-chip RISC processor. This RISC processor will have an internal view
of the register and memory blocks. This view is one large contiguous and addressable range, where the register block maps
starting at offset 0xC0000000. On the other hand, host processors have two entirely different views. When the BCM5722
Ethernet controller is configured in standard mode, the register block is mapped into a 64K host memory range. The host
processor must use a memory window or indirect mode to access the memory block. A Flat mode configuration maps both
the memory and register blocks into 32 MB of address space. Flat mode ties up a much larger range of host memory
addresses. It is fundamental to understand that the register and memory blocks are not necessarily tied together. The PCI
mode and processor context all affect how software views both blocks (see the following figure).
Figure 37: Local Contexts
0x00000000
0xC0000000
0x0002000
Internal
Memory
PCI Configuration
Space Shadow
Priority Mailboxes
1
Registers
Rx CPU
Scratchpad
Memory Window
Tx CPU
Scratchpad
ROM
Rsvd
0xC0000400
1
0xC0008000
0xC0000100
0xC0000200
1
0xC0010000
0xC0030000
Rsvd
BCM57XX
Ethernet
Controller
0xC0038000
Local Memory
Block
Register Block
. The high-priority mailboxes are at offset 0x200 through 0x3FF for host standard and flat modes, and the low-priority
mailboxes are at offset 0x5800 through 0x59FF for indirect mode.
. The local memory addresses in this diagram apply to standard and internal views only. Flat mode decodes a different address
range. Refer to the section on memory maps and pool configuration.
To Next Page
Loading...