BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 107 PCI Document 5722-PG101-R
Section 9: PCI
CONFIGURATION SPACE
DESCRIPTION
PCI, PCI-X, and PCIe devices must implement sixteen 32-bit PCI registers. These registers are required for a device to have
PCI compliance. The format and layout of these registers is defined in the PCI 2.2 specification. Capability registers provide
system BIOS and Operating Systems visibility into a set of optional features, which devices may implement. Although the
capability registers are not required, the structure and mechanism for chaining auxiliary capabilities is defined in the PCI
specification. Both software and BIOS must implement algorithms to fetch and program capabilities fields accordingly. Refer
to section 6.7 of the PCI SIIG 2.2 specification. Additional PCI configuration space may be used for device-specific registers.
However, device-specific registers are not exposed to system software, according to a specification/standard. System
software cannot probe device specific registers without a predetermined understanding of the device and its functionality. In
summary, three types of PCI configuration space registers may be exposed by any particular device:
• Required
• Optional capabilities
• Device specific
Network devices implement large quantities of registers, and these registers could consume huge amounts of PCI
configuration space. PCI configuration access is not very efficient, on a performance basis. For example, Intel x86
architectures use two I/O mapped I/O addresses 0xCF8 and 0xCFC for host-based access to PCI configuration space.
Should a host device driver access these I/O addresses on every device read/write, CPU overhead would grow greatly.
Generally, host device drivers should not use PCI configuration space for standard I/O and control programming. There is
one special case—Universal Network Device Interface (UNDI) drivers. UNDI drivers may not have access to host memory
mapped registers when operating in real-mode; thus, an indirect mode of access is necessary. The BCM5722 Ethernet
controller implements a PCI indirect mode for memory, registers, and mailboxes access. A specific example of a device
driver, which uses indirect mode, is the Preboot Execution (PXE) driver. PXE drivers may be stored in either option ROMs
or directly in the system BIOS.
Most host device drivers use register blocks, which are mapped into host memory. Memory Mapped I/O is an efficient
mechanism for PCI devices to use system resources. The type and extent of this memory mapping depends upon the MAC’s
configuration (see the operational characteristics subsection). A typical PCI device will decode a range of physical (bus)
addresses, which do not conflict with physical memory or other PCI devices. Each device on the PCI bus will request a range
of physical memory, and the PnP BIOS will assign mutually exclusive resources to that device. The size and range of
resource is based upon each device’s hardwired programming of the BAR. The BCM5722 Ethernet controller implements
two modes of memory mapped I/O—Standard and Flat. I/O mapped I/O is not supported by the BCM5722 Ethernet
controller, and there are no I/O space registers.
Note: The PCI BAR 0 register is only reset to 0 after a hard reset, otherwise it maintains its value over GRC and
PCI resets.
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