Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Write DMA Control Registers Page 314
WRITE DMA CONTROL REGISTERS
WRITE DMA MODE REGISTER (OFFSET 0X4C00)
Table 312: Write DMA Control Registers
Offset Registers
0x4c00–0x4c03 Write DMA Mode
0x4c04–0x4c07 Write DMA Status
0x4c08–0x4c4c WDMA debug register 0–18 (BCM5906 only)
0x4c4f–0x4fff Reserved
Note: The BCM5906 WDMA debug register is read-only. Reads to this register return the internal state value. Do
not write to this register.
Table 313: Write DMA Mode Register (Offset 0x4C00)
Bit Field Description Init Access
31:30 Reserved – 0 RO
29 Status Tag Fix (CQ12384)
Enable (BCM5755,
BCM5755M, BCM5906,
BCM5906M only)
• 1 = Enable Fix. Device will send out the status block
before the interrupt message.
• 0 = Disable Fix. Device will send out the interrupt
message before the status block.
0R/W
Reserved (other devices) – 0 RO
28:19 Reserved – RO
18 Swap Test Enable When this bit is set, swap test mode will be enabled and
bits 17 to 12 can be used to test different byte/word swap
settings.
0R/W
17 HC Byte Swap Byte swap control for status words. 0 R/W
16 HC Word Swap Word swap control for status words. 0 R/W
15 BD Byte Swap Byte swap control for return BDs. 0 R/W
14 BD Word Swap Word swap control for return BDs. 0 R/W
13 Data Byte Swap Byte swap control for data. 0 R/W
12 Data Word Swap Word swap control for data. 0 R/W
11 Software Byte Swap
Control
To override byte enables with all 1s. 0 R/W
10 Receive Accelerate Mode The write DMA-to-PCI request length is the available data
size in the PCI RX FIFO.
Set to 1—The write DMA-to-PCI request length is the
maximum length of the current transaction, regardless of
the available data size in PCI RX FIFO.
This mode cannot be used in slow core clock
environment. Disable this mode before switching to slow
core clock mode.
0R/W
Reserved (BCM5906 only) – 0 RO
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