Broadcom BCM5722 - Page 455

Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R PCIe Registers Page 396
19 Enable Pending
Completion Packet
Issue Fix CQ10452
Enable this fix to wake up from L1 and flush out pending
TLP.
• 1 = Disable fix
• 0 = Enable fix
0R/W
18 PLL REFSEL Switch
Control CQ11011
Enable this fix to allow PLL source clock to switch to local
crystal at the absence of PCIe ref clock.
• 1 = Enable switch
• 0 = Disable switch
1R/W
17 Reserved – 0 R/W
16 Power Management
Control
Enable power management clock switching (allows core
clk to be automatically muxed into PCIe clocks).
1R/W
15 Power Down SerDes
Transmitter
Forces the SerDes transmitter into the low-power state
(when cleared, the transmitter power state is controlled
by the power management state machine).
0R/W
14 Power Down SerDes
PLL
Forces the SerDes PLL into the low-power state (when
cleared, the PLL power state is controlled by the power
management state machine).
0R/W
13 Power Down SerDes
Receiver
Forces the SerDes receiver into the low-power state
(when cleared, receiver power state is controlled by
power management state machine).
0R/W
12 Enable Beacon Enable transmission of In-band Beacon signal when
waking system.
1R/W
11 Automatic Timer
Threshold Enable
• 1 = Enable automatic calculation of ACK Latency and
Replay Timeout Values.
• 0 = Use register values for ACK Latency and Replay
Timeout.
1R/W
10 Enable DLLP Timeout
Mechanism
When set to 1, link is retrained if the DLLP receive timer
expires without receiving a valid DLLP.
1R/W
9 Check Receive Flow
Control Credits
Check receive flow control credit consumption and report
receive overflow errors when enabled.
1R/W
8 Link Enable Enable the data link layer functions. 1 R/W
7:0 Power Management
Control
These bits enable automatic power management
functions (power up/down or clock gating):
• 7 = Enable Active State power management.
• 6 = Enable PCI-PM power management (clearing this
bit does not disable PM_PME message generation).
• 5 = Enable SerDes transmitter power management.
• 4 = Enable SerDes PLL power management.
• 3 = Enable SerDes receiver power management.
• 2 = Enable transaction layer power management
(clock gating).
• 1 = Enable data link layer power management (clock
gating).
• 0 = Enable physical layer power management (clock
gating).
0xFF R/W
Table 439: Data Link Control Register (Offset 0x7D00) (Cont.)
Bit Field Description Init Access