BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 501 Transceiver Registers (BCM5906/BCM5906M) Document 5722-PG101-R
SPD Mask
When this bit is set, changes in operating speed does not generate an interrupt.
Link Mask
When this bit is set, changes in link status does not generate an interrupt.
Interrupt Mask
Master interrupt mask. When this bit is set, no interrupts will be generated, regardless of the state of the other mask bits.
Cable Disconnect Link Change
This bit is set to 1 when a cable is being removed after a link has been established. No interrupt is
issued if the link drops but the cable is not removed. An interrupt is issued immediately when the cable is removed. It is a
self-clearing (SC) bit like the rest of the interrupt bits.
Global Interrupt Indicator
A 1 indicates an Interrupt is present within the PHY.
FDX Change
A 1 indicates a change of duplex status since last register read. Register read clears the bit.
SPD Change
A 1 indicates a change of speed status since last register read. Register read clears the bit.
Link Change
A 1 indicates a change of link status since last register read. Register read clears the bit.
Interrupt Status
Represents status of the INTR pin. A 1 indicates that the interrupt mask is off and that one or more of the change bits are
set. Register read clears the bit.
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