Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Power Management Page 138
Device State D0 (Active)
Host software has initialized the MAC hardware blocks. The RX and TX data paths are ready to send/receive Ethernet
packets. The PCI block is available to DMA packets to host memory. This is a full power ACPI operational state. Host
software/drivers must follow the initialization procedure (see “Initialization” on page 82) to move the MAC into a D0 active
state.
When the BCM5722 NetXtreme devices detect that main power is lost and it's still in the D0 state, it will reset itself to the D3
(Cold) state and then operate in 10/100 mode, like the OOB WOL state.
Device State D3 (Hot)
The MAC’s configuration space and memory mapped I/O blocks are accessible in D3 hot state. The PCI I/O drivers are still
powered by slot power in this state. However, host software has switched the MAC to use PCI Vaux for VDD_CORE and
VDD_IO. GPIO pins 0, 1, and 2 are configured before the transition to this state. The RX and TX RISC processor clocks
have been stopped in this state. The core clock remains active so PCI transactions may be processed by the MAC (see “PCI
Clock Control Register (Offset 0x74)” on page 207). This is a low-power state where some key components have been
powered down. The physical layer auto-advertises 10 Mbps capability in this state, and link is set to 10 Mbps half or full-
duplex. The PHY is configured for WOL mode. WOL pattern filters are initialized and active; the MAC will process Magic
Packets™. The host chipset implements the power management policy for the PCI bus; the MAC driver does not influence
the PCI Vaux or Slot power supply.
Device State D3 (Cold)
The MAC is completely powered by PCI Vaux in D3 cold. PCI configuration space and memory mapped I/O are not available.
The only portion of the MAC active is the WOL pattern and Magic Packet filters
2
. The MAC will assert a PME in this state
and indicate to the host bridge that a wake up event has occurred. The host bridge will normally provide PCI Slot power and
then reset the device. GPIO pins 0, 1, and 2 are configured the same as D3 hot. Host software does not differentiate between
D3 hot/cold. The MAC and PHY will not consume more than 375 mA in this mode. The integrated PHY must negotiate for
10 Mbps half/duplex speed. The PHY WOL mode is configured.
WAKE ON LAN
See “Wake on LAN Mode/Low-Power” on page 158.
Note: The drivers should use configuration cycles (not the memory write cycles) to write to the PMCSR register
at offset 0x4C for putting the device in D3 Hot state.
2. Magic Packet™ is a registered trade mark of AMD.
Note: The PCIe devices support the PCIe power management which is compatible with PCI bus power
management.
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