Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R Device Control Page 82
Section 8: Device Control
INITIALIZATION
DESCRIPTION
This section provides programmers a procedure for initializing the NetXtreme family of devices. There is a specific sequence
of steps that must be taken to enable this device. This section assumes the host programmer can allocate physical memory
for various control blocks using OS/RTOS specific methods. Ring Control Blocks (RCBs) and Buffer Descriptors (BDs) all
require host physical addresses; the MAC uses bus-master DMA to move packet data to host memory. The methods for
allocation and de-allocation of host physical memory are beyond this document’s scope.
INITIALIZATION PROCEDURE
This section lists the initializing procedure for the MAC portion of the NetXtreme family of devices.
1. Enable MAC memory space decode and bus mastering (optional). If the device has not been initialized previously (power
on reset), the host software must enable these bits to issue the core clock reset in Step 7. Set the Bus_Master and
Memory_Space bits in the PCI Configuration Space Command register (see “Command Register (Offset 0x04)” on
page 190).
2. Disable interrupts (optional). If the device has not been initialized previously (power-on reset), the host software should
disable and clear interrupts prior to the core_clock reset. Set the Mask_PCI_Interrupt_Output and Clear_Interrupt_INTA
bits in the Miscellaneous Host Control register (see “Miscellaneous Host Control Register (Offset 0x68)” on page 204).
3. Save the PCI Cache Line Size register and PCI Subsystem Vendor ID registers (see “Cache Line Size Register (Offset
0x0C)” on page 192 and “Subsystem ID Register (Offset 0x2E)” on page 194) in the PCI configuration space to
temporary variables. These registers must be restored after a core clock reset.
4. Acquire the NVRAM lock by setting the SET1 bit of the Software Arbitration register (see “Software Arbitration Register
(Offset 0x7020)” on page 374), and then waiting for the ARB_WON1 bit to be set.
5. Enable the Memory Arbiter as specified in Step 11. Also initialize the Misc Host Control register as specified in Step 12.
6. Write the T3_MAGIC_NUMBER (i.e., 0x4B657654) to the device memory at offset 0xB50 to notify the bootcode that the
following reset is a warm reset (driver initiated core_clock reset).
7. Reset the core clocks. Set the CORE_CLock_Blocks-Reset bit in the General Control Miscellaneous Configuration
register (see “Miscellaneous Configuration Register (Offset 0x6804)” on page 335). The GPHY_Power_Down_Override
bit (bit-26) should also be set to 1. The Disable_GRC_Reset_on_PCI-E_Block bit (bit-29) should also be set to 1.
8. Wait for core-clock reset to complete. Software should wait 100 ms for PCIe systems. The core clock reset will disable
indirect mode and flat/standard modes—software cannot poll the core-clock reset bit to de-assert, since the local memory
interface is disabled by the reset.
9. Disable interrupts. Set the Mask_PCI_Interrupt_Output bit in the Miscellaneous Host Control register (see
“Miscellaneous Host Control Register (Offset 0x68)” on page 204). The bit was reset after the core_clock reset, and
interrupts must be masked off again.
10. Enable MAC memory space decode and bus mastering. Set the Bus_Master and Memory_Space bits in the PCI
Configuration Space Command register (see “Command Register (Offset 0x04)” on page 190).
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