BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 83 Initialization Document 5722-PG101-R
11. Enable the MAC memory arbiter. Set the Enable bit in the Memory Arbiter Mode register (see “Memory Arbiter Mode
Register (Offset 0x4000)” on page 301).
12. Initialize the Miscellaneous Host Control register (see “Miscellaneous Host Control Register (Offset 0x68)” on page 204):
a. Set Endian Word Swap (optional). When the host processor architecture is big endian, the MAC may wordswap data,
when acting as a PCI target device. Set the Enable_Endian_Word_Swap bit in the Miscellaneous Host Control
register.
b. Set Endian Byte Swap (optional). When the host processor architecture is big-endian, the MAC may byteswap data,
when acting as a PCI target device. Set the Enable_Endian_Byte_Swap bit in the Miscellaneous Host Control
register.
c. Enable the indirect register pairs (see “Indirect Mode” on page 113). Set the Enable_Indirect_Access bit in the
Miscellaneous Host Control register.
d. Enable the PCI State register to allow the device driver read/write access by setting the Enable_PCI_State_Register
bit in the Miscellaneous Host Control register
e. Enable the PCI Clock Control register (see “PCI Clock Control Register (Offset 0x74)” on page 207) to allow the
device driver read/write access by setting the Enable_Clock_Control_Register bit in the Miscellaneous Host Control
register (see “Miscellaneous Host Control Register (Offset 0x68)” on page 204).
13. Set Byte_Swap_Non_Frame_Data and Byte_Swap_Data in the General Mode Control register (see “Mode Control
Register (Offset 0x6800)” on page 333).
14. Set Word_Swap_Data and Word_Swap_Non_Frame_Data (Optional). When the host processor architecture is little-
endian, set these additional bits in the General Mode Control register (see “Mode Control Register (Offset 0x6800)” on
page 333).
15. Configure the Port Mode bits of the Ethernet MAC Mode register (see “Ethernet MAC Mode Register (Offset 0x400)” on
page 245) to GMII for all devices supporting copper Ethernet Media. Wait for 40 ms.
16. Poll for bootcode completion. The device driver should poll the general communication memory at 0xB50 (see “Memory
Maps and Pool Configuration” on page 101) for the one’s complement of the T3_MAGIC_NUMBER (i.e., 0xB49A89AB).
The bootcode should complete initialization within 1000 ms for Flash devices and 10000 ms for SEEPROM devices.
17. Enable/Disable any required PCIe bug fixes. Enable the PCIe bug fixes by setting the bits 25 and 29 of the “TLP Control
Register (Offset 0x7C00)” on page 383 without modifying the other bits of this register. Please refer to the Errata
document for information on any other errata that should be worked around by enabling/disabling the control bits of chip
bug fixes.
18. Enable Tagged Status Mode (optional) by setting the Enable_Tagged_Status_Mode bit of the Miscellaneous Host
Control register (see “Miscellaneous Host Control Register (Offset 0x68)” on page 204). (For further information on
Tagged Status Mode see “Interrupt Processing” on page 177).
19. Restore the PCI Cache Line Size and PCI Subsystem Vendor ID registers (see “Cache Line Size Register (Offset 0x0C)”
on page 192 and “Subsystem Vendor ID Register (Offset 0x2C)” on page 194) in the PCI configuration space. These
registers were cleared by the core clock reset.
20. Clear the driver status block memory region. Write zeros to the host memory region where the status block will be DMAed
(see “Status Block” on page 53).
Note: This register is not cleared by the core clock reset above.
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