Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R PCIe Registers Page 386
19 Ignore_hotplug_msg Allow the device to ignore Hot-Plug Messages
• 0 = Decode Hot-Plug Message
• 1 = Ignore Hot-Plug Message
RW Core 1
18–16 Msi_multmsg_capable MSI Multiple Message Capable. This field is
copied over to the MSI Control Field in the
Config.vhd. System software read the
Multiple Message Capable field to determine
the number of requested messages.
• 000 = 1
• 001 = 2
• 010 = 4
• 011 = 8
• 100 = 16
The BCM5722, BCM5755, BCM5755M,
BCM5756M, BCM5757, BCM5754,
BCM5754M, BCM5787, and BCM5787M
devices can only request a maximum of 1 MSI
Message.
RW Core 0x0
15:12 Data_select_limit This parameter is used in the PCIe Power
Budget Capability Structure to determine the
number of Power Conditions that the device
support. Default is 4 which means that the
device supports four different types of Power
Conditions. The BCM5722, BCM5755,
BCM5755M, BCM5756M, BCM5757,
BCM5754, BCM5754M, BCM5787, and
BCM5787M devices can support up to 8
different power conditions.
RW Core 0x0
11 Enable_pcie_1_1_pl This bit enables PCIe 1.1 compliance
changes in the Physical Layer.
• 1 = Enable Compliance
• 0 = Disable Compliance
RW Core 1
10 Enable_pcie_1_1_dl This bit enables PCIe1.1 compliance changes
in the Data Link Layer. This bit is not used.
• 1 = Enable Compliance
• 0 = Disable Compliance
RW Core 1
9 Enable_pcie_1_1_tl This bit enables PCIe1.1 compliance changes
in the Transaction Layer specifically for
masking training error from the physical layer
• 1 = Mask Training Error
• 0 = Allow Training Error to log
RW Core 1
8–7 Reserved Spares RW Core 0x1
6 Pcie_power_budget_cap_enable This bit is used to control the present of the
PCIe Power Budget Capability Structure.
• 1 = Enable
• 0 = Disable
RW Core 0
Table 414: Transaction Configuration Register (0x7C04) (Cont.)
Bit Field Description Access Reset Init
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