Programmer’s Guide BCM5722
10/15/07
Broadcom Corporation
Document 5722-PG101-R General Control Registers Page 334
11 Allow Bad Frames The RX MAC forwards illegal frames to the NIC and marks
them as such instead of discarding them. The frames are
queued based on default class and interrupt distribution
queue number as specified in “Receive List Placement
Configuration Register (Offset 0x2010)” on page 283).
0R/W
10 Reserved – 0
9 No Frame Cracking Turn off all frame cracking functionality in both the read DMA
engine and the MAC receive engine. On receive, the TCP/
UDP checksum field is replaced by raw checksum for the
whole frame except the Ethernet header.
On transmit, IP and TCP/UDP checksum generation is always
disabled when this bit is set. Also, the raw checksum is
calculated over the entire frame except the Ethernet header
and CRC.
0R/W
8–6 Reserved – 000 RO
5 Word Swap Data Word swap data when DMAing it across the PCI bus. 0 R/W
4 Byte Swap Data Byte swap data when DMAing it across the PCI bus. 0 R/W
3Reserved – 0 RO
2 Word Swap Non-frame Data Word swap control structures (buffer descriptors, statistics)
and data when DMAing them across the PCI bus.
0R/W
1 Byte Swap Non-frame Data Byte swap control structures (buffer descriptors, statistics)
when DMAing them across the PCI bus.
0R/W
0Reserved – 0 RO
Table 342: Mode Control Register (Offset 0x6800) (Cont.)
Bit Field Description Init Access
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