BCM5722 Programmer’s Guide
10/15/07
Broadcom Corporation
Page 87 Initialization Document 5722-PG101-R
40. Configure the MAC unicast address. See “MAC Address Setup/Configuration” on page 96 for a full description of unicast
MAC address initialization.
41. Configure random backoff seed for transmit. See the Ethernet Transmit Random Backoff register (see “Ethernet
Transmit Random Backoff Register (Offset 0x438)” on page 250). Broadcom recommends using the following algorithm:
Seed = (MAC_ADDR[0] + MAC_ADDR[1] + MAC_ADDR[2] + MAC_ADDR[3] + MAC_ADDR[4] +
MAC_ADDR[5]) & 0x3FF
42. Configure the Message Transfer Unit MTU size. The MTU sets the upper boundary on RX packet size; packets larger
than the MTU are marked oversized and discarded by the RX MAC. The MTU bit field in the Receive MTU Size register
(see “Receive MTU Size Register (Offset 0x43C)” on page 250) must be configured before RX traffic is accepted. Host
software should account for the following variables when calculating the MTU:
•VLAN TAG
• CRC
• Jumbo Frames Enabled
43. Configure IPG for transmit. The Transmit MAC Lengths register (see “Transmit MAC Lengths Register (Offset 0x464)”
on page 254) contains three bit fields: IPG_CRS_Length, IPG_Length, and Slot_Time_Length. The value the 0x2620
should be written into this register.
44. Configure default RX return ring for non-matched packets. The MAC has a rules checker, and packets do not always
have a positive match. For this situation, host software must specify a default ring, where RX packet should be placed.
The bit field is located in the Receive Rules Configuration register (see “Receive Rules Configuration Register (Offset
0x500)” on page 258).
45. Configure the number of Receive Lists. The Receive List Placement Configuration register (see “Receive List Placement
Configuration Register (Offset 0x2010)” on page 283) allows host software to initialize QOS rules checking. For example,
a value of 0x181 breaks down as follows:
• One interrupt distribution list
• Sixteen active lists
• One bad frames class
46. Write the Receive List Placement Statistics mask. Write 0xFFFFFF (24 bits) to the Receive List Placement Stats Enable
Mask register (see “Receive List Placement Statistics Enable Mask Register (Offset 0x2018)” on page 284).
47. Enable RX statistics. Assert the Statistics_Enable bit in the Receive List Placement Control register (see “Receive List
Placement Statistics Control Register (Offset 0x2014)” on page 283).
48. Enable the Send Data Initiator mask. Write 0xFFFFFF (24 bits) to the Send Data Initiator Enable Mask register (see
“Send Data Initiator Statistics Enable Mask Register (Offset 0x0C0C)” on page 270).
49. Enable TX statistics. Assert the Statistics_Enable and Faster_Statistics_Update bits in the Send Data Initiator Control
register (0x0C08)
50. Disable the host coalescing engine. Software needs to disable the host coalescing engine before configuring its
parameters. Write 0x0000 to the Host Coalescing Mode register (see “Host Coalescing Mode Register (Offset 0x3C00)”
on page 294).
51. Poll 20 ms for the host coalescing engine to stop. Read the Host Coalescing Mode register (see “Host Coalescing Mode
Register (Offset 0x3C00)” on page 294) and poll for 0x0000. The engine was stopped in the previous step.
52. Configure the host coalescing tick count. The Receive Coalescing Ticks and Send Coalescing Ticks registers (see
“Receive Coalescing Ticks Registers (Offset 0x3C08)” on page 295 and “Send Coalescing Ticks Register (Offset
0x3C0C)” on page 295) specify the number of clock ticks elapsed before an interrupt is driven. The clock begins ticking
after RX/TX activity. Broadcom recommends the settings shown in Table 38 on page 88.
Note: An incorrectly configured IPG will introduce far end receive errors on the MAC’s link partner.
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